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@@ -93,13 +93,13 @@
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(FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
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/* FLEXCAN control register 2 (CTRL2) bits */
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-#define FLEXCAN_CRL2_ECRWRE BIT(29)
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-#define FLEXCAN_CRL2_WRMFRZ BIT(28)
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-#define FLEXCAN_CRL2_RFFN(x) (((x) & 0x0f) << 24)
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-#define FLEXCAN_CRL2_TASD(x) (((x) & 0x1f) << 19)
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-#define FLEXCAN_CRL2_MRP BIT(18)
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-#define FLEXCAN_CRL2_RRS BIT(17)
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-#define FLEXCAN_CRL2_EACEN BIT(16)
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+#define FLEXCAN_CTRL2_ECRWRE BIT(29)
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+#define FLEXCAN_CTRL2_WRMFRZ BIT(28)
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+#define FLEXCAN_CTRL2_RFFN(x) (((x) & 0x0f) << 24)
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+#define FLEXCAN_CTRL2_TASD(x) (((x) & 0x1f) << 19)
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+#define FLEXCAN_CTRL2_MRP BIT(18)
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+#define FLEXCAN_CTRL2_RRS BIT(17)
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+#define FLEXCAN_CTRL2_EACEN BIT(16)
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/* FLEXCAN memory error control register (MECR) bits */
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#define FLEXCAN_MECR_ECRWRDIS BIT(31)
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@@ -221,7 +221,7 @@ struct flexcan_regs {
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u32 imask1; /* 0x28 */
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u32 iflag2; /* 0x2c */
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u32 iflag1; /* 0x30 */
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- u32 crl2; /* 0x34 */
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+ u32 ctrl2; /* 0x34 */
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u32 esr2; /* 0x38 */
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u32 imeur; /* 0x3c */
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u32 lrfr; /* 0x40 */
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@@ -825,7 +825,7 @@ static int flexcan_chip_start(struct net_device *dev)
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{
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struct flexcan_priv *priv = netdev_priv(dev);
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struct flexcan_regs __iomem *regs = priv->base;
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- u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
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+ u32 reg_mcr, reg_ctrl, reg_ctrl2, reg_mecr;
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int err, i;
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/* enable module */
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@@ -928,9 +928,9 @@ static int flexcan_chip_start(struct net_device *dev)
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* and Correction of Memory Errors" to write to
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* MECR register
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*/
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- reg_crl2 = flexcan_read(®s->crl2);
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- reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
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- flexcan_write(reg_crl2, ®s->crl2);
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+ reg_ctrl2 = flexcan_read(®s->ctrl2);
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+ reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE;
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+ flexcan_write(reg_ctrl2, ®s->ctrl2);
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reg_mecr = flexcan_read(®s->mecr);
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reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
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