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@@ -1219,6 +1219,40 @@ struct atom_gfx_info_v2_3 {
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uint32_t rm21_sram_vmin_value;
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uint32_t rm21_sram_vmin_value;
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};
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};
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+struct atom_gfx_info_v2_4 {
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+ struct atom_common_table_header table_header;
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+ uint8_t gfxip_min_ver;
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+ uint8_t gfxip_max_ver;
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+ uint8_t gc_num_se;
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+ uint8_t max_tile_pipes;
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+ uint8_t gc_num_cu_per_sh;
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+ uint8_t gc_num_sh_per_se;
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+ uint8_t gc_num_rb_per_se;
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+ uint8_t gc_num_tccs;
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+ uint32_t regaddr_cp_dma_src_addr;
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+ uint32_t regaddr_cp_dma_src_addr_hi;
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+ uint32_t regaddr_cp_dma_dst_addr;
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+ uint32_t regaddr_cp_dma_dst_addr_hi;
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+ uint32_t regaddr_cp_dma_command;
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+ uint32_t regaddr_cp_status;
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+ uint32_t regaddr_rlc_gpu_clock_32;
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+ uint32_t rlc_gpu_timer_refclk;
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+ uint8_t active_cu_per_sh;
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+ uint8_t active_rb_per_se;
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+ uint16_t gcgoldenoffset;
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+ uint32_t rm21_sram_vmin_value;
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+ uint16_t gc_num_gprs;
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+ uint16_t gc_gsprim_buff_depth;
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+ uint16_t gc_parameter_cache_depth;
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+ uint16_t gc_wave_size;
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+ uint16_t gc_max_waves_per_simd;
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+ uint16_t gc_lds_size;
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+ uint8_t gc_num_max_gs_thds;
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+ uint8_t gc_gs_table_depth;
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+ uint8_t gc_double_offchip_lds_buffer;
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+ uint8_t gc_max_scratch_slots_per_cu;
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+};
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+
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/*
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/*
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***************************************************************************
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***************************************************************************
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Data Table smu_info structure
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Data Table smu_info structure
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