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@@ -47,6 +47,17 @@ static const char *ssi_sel_clks[] = { "spll_gate", "mpll", };
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk *clk[IMX27_CLK_MAX];
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static struct clk_onecell_data clk_data;
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static struct clk_onecell_data clk_data;
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+static struct clk ** const uart_clks[] __initconst = {
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+ &clk[IMX27_CLK_PER1_GATE],
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+ &clk[IMX27_CLK_UART1_IPG_GATE],
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+ &clk[IMX27_CLK_UART2_IPG_GATE],
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+ &clk[IMX27_CLK_UART3_IPG_GATE],
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+ &clk[IMX27_CLK_UART4_IPG_GATE],
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+ &clk[IMX27_CLK_UART5_IPG_GATE],
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+ &clk[IMX27_CLK_UART6_IPG_GATE],
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+ NULL
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+};
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+
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static void __init _mx27_clocks_init(unsigned long fref)
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static void __init _mx27_clocks_init(unsigned long fref)
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{
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{
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BUG_ON(!ccm);
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BUG_ON(!ccm);
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@@ -163,6 +174,8 @@ static void __init _mx27_clocks_init(unsigned long fref)
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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clk_prepare_enable(clk[IMX27_CLK_EMI_AHB_GATE]);
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+ imx_register_uart_clocks(uart_clks);
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+
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imx_print_silicon_rev("i.MX27", mx27_revision());
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imx_print_silicon_rev("i.MX27", mx27_revision());
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}
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}
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