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@@ -3226,13 +3226,6 @@ static void gfx_v8_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
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udelay(50);
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udelay(50);
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}
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}
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-static int gfx_v8_0_cp_compute_start(struct amdgpu_device *adev)
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-{
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- gfx_v8_0_cp_compute_enable(adev, true);
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-
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- return 0;
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-}
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-
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static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
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static int gfx_v8_0_cp_compute_load_microcode(struct amdgpu_device *adev)
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{
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{
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const struct gfx_firmware_header_v1_0 *mec_hdr;
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const struct gfx_firmware_header_v1_0 *mec_hdr;
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@@ -3802,9 +3795,7 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev)
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WREG32(mmCP_PQ_STATUS, tmp);
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WREG32(mmCP_PQ_STATUS, tmp);
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}
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}
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- r = gfx_v8_0_cp_compute_start(adev);
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- if (r)
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- return r;
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+ gfx_v8_0_cp_compute_enable(adev, true);
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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for (i = 0; i < adev->gfx.num_compute_rings; i++) {
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
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struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
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