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@@ -57,7 +57,6 @@ static void si_ih_disable_interrupts(struct amdgpu_device *adev)
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static int si_ih_irq_init(struct amdgpu_device *adev)
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{
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- int ret = 0;
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int rb_bufsz;
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u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
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u64 wptr_off;
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@@ -72,18 +71,15 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
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WREG32(IH_RB_BASE, adev->irq.ih.gpu_addr >> 8);
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rb_bufsz = order_base_2(adev->irq.ih.ring_size / 4);
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- ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
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- IH_WPTR_OVERFLOW_CLEAR |
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- (rb_bufsz << 1));
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-
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- ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;
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+ ih_rb_cntl = IH_WPTR_OVERFLOW_ENABLE |
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+ IH_WPTR_OVERFLOW_CLEAR |
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+ (rb_bufsz << 1) |
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+ IH_WPTR_WRITEBACK_ENABLE;
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wptr_off = adev->wb.gpu_addr + (adev->irq.ih.wptr_offs * 4);
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WREG32(IH_RB_WPTR_ADDR_LO, lower_32_bits(wptr_off));
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WREG32(IH_RB_WPTR_ADDR_HI, upper_32_bits(wptr_off) & 0xFF);
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-
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WREG32(IH_RB_CNTL, ih_rb_cntl);
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-
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WREG32(IH_RB_RPTR, 0);
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WREG32(IH_RB_WPTR, 0);
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@@ -93,10 +89,9 @@ static int si_ih_irq_init(struct amdgpu_device *adev)
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WREG32(IH_CNTL, ih_cntl);
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pci_set_master(adev->pdev);
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-
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si_ih_enable_interrupts(adev);
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- return ret;
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+ return 0;
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}
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static void si_ih_irq_disable(struct amdgpu_device *adev)
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@@ -165,9 +160,7 @@ static int si_ih_sw_init(void *handle)
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if (r)
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return r;
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- r = amdgpu_irq_init(adev);
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-
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- return r;
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+ return amdgpu_irq_init(adev);
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}
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static int si_ih_sw_fini(void *handle)
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@@ -182,14 +175,9 @@ static int si_ih_sw_fini(void *handle)
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static int si_ih_hw_init(void *handle)
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{
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- int r;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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- r = si_ih_irq_init(adev);
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- if (r)
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- return r;
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-
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- return 0;
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+ return si_ih_irq_init(adev);
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}
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static int si_ih_hw_fini(void *handle)
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@@ -229,12 +217,10 @@ static bool si_ih_is_idle(void *handle)
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static int si_ih_wait_for_idle(void *handle)
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{
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unsigned i;
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- u32 tmp;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < adev->usec_timeout; i++) {
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- tmp = RREG32(SRBM_STATUS) & SRBM_STATUS__IH_BUSY_MASK;
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- if (!tmp)
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+ if (si_ih_is_idle(handle))
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return 0;
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udelay(1);
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}
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