|
@@ -313,7 +313,7 @@ static bool dwc2_iddig_filter_enabled(struct dwc2_hsotg *hsotg)
|
|
|
* Do core a soft reset of the core. Be careful with this because it
|
|
|
* resets all the internal state machines of the core.
|
|
|
*/
|
|
|
-int dwc2_core_reset(struct dwc2_hsotg *hsotg)
|
|
|
+int dwc2_core_reset(struct dwc2_hsotg *hsotg, bool skip_wait)
|
|
|
{
|
|
|
u32 greset;
|
|
|
int count = 0;
|
|
@@ -369,7 +369,7 @@ int dwc2_core_reset(struct dwc2_hsotg *hsotg)
|
|
|
}
|
|
|
} while (!(greset & GRSTCTL_AHBIDLE));
|
|
|
|
|
|
- if (wait_for_host_mode)
|
|
|
+ if (wait_for_host_mode && !skip_wait)
|
|
|
dwc2_wait_for_mode(hsotg, true);
|
|
|
|
|
|
return 0;
|
|
@@ -500,7 +500,7 @@ int dwc2_core_reset_and_force_dr_mode(struct dwc2_hsotg *hsotg)
|
|
|
{
|
|
|
int retval;
|
|
|
|
|
|
- retval = dwc2_core_reset(hsotg);
|
|
|
+ retval = dwc2_core_reset(hsotg, false);
|
|
|
if (retval)
|
|
|
return retval;
|
|
|
|