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@@ -529,34 +529,35 @@ int gic_cpu_if_down(unsigned int gic_nr)
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* this function, no interrupts will be delivered by the GIC, and another
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* platform-specific wakeup source must be enabled.
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*/
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-static void gic_dist_save(unsigned int gic_nr)
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+static void gic_dist_save(struct gic_chip_data *gic)
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{
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unsigned int gic_irqs;
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void __iomem *dist_base;
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int i;
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- BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
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+ if (WARN_ON(!gic))
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+ return;
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- gic_irqs = gic_data[gic_nr].gic_irqs;
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- dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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+ gic_irqs = gic->gic_irqs;
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+ dist_base = gic_data_dist_base(gic);
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if (!dist_base)
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return;
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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- gic_data[gic_nr].saved_spi_conf[i] =
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+ gic->saved_spi_conf[i] =
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readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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- gic_data[gic_nr].saved_spi_target[i] =
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+ gic->saved_spi_target[i] =
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readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
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- gic_data[gic_nr].saved_spi_enable[i] =
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+ gic->saved_spi_enable[i] =
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readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
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- gic_data[gic_nr].saved_spi_active[i] =
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+ gic->saved_spi_active[i] =
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readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
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}
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@@ -567,16 +568,17 @@ static void gic_dist_save(unsigned int gic_nr)
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* handled normally, but any edge interrupts that occured will not be seen by
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* the GIC and need to be handled by the platform-specific wakeup source.
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*/
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-static void gic_dist_restore(unsigned int gic_nr)
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+static void gic_dist_restore(struct gic_chip_data *gic)
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{
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unsigned int gic_irqs;
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unsigned int i;
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void __iomem *dist_base;
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- BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
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+ if (WARN_ON(!gic))
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+ return;
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- gic_irqs = gic_data[gic_nr].gic_irqs;
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- dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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+ gic_irqs = gic->gic_irqs;
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+ dist_base = gic_data_dist_base(gic);
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if (!dist_base)
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return;
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@@ -584,7 +586,7 @@ static void gic_dist_restore(unsigned int gic_nr)
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writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
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- writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
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+ writel_relaxed(gic->saved_spi_conf[i],
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dist_base + GIC_DIST_CONFIG + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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@@ -592,85 +594,87 @@ static void gic_dist_restore(unsigned int gic_nr)
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dist_base + GIC_DIST_PRI + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
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- writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
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+ writel_relaxed(gic->saved_spi_target[i],
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dist_base + GIC_DIST_TARGET + i * 4);
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
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- writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
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+ writel_relaxed(gic->saved_spi_enable[i],
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dist_base + GIC_DIST_ENABLE_SET + i * 4);
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}
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for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
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- writel_relaxed(gic_data[gic_nr].saved_spi_active[i],
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+ writel_relaxed(gic->saved_spi_active[i],
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dist_base + GIC_DIST_ACTIVE_SET + i * 4);
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}
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writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
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}
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-static void gic_cpu_save(unsigned int gic_nr)
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+static void gic_cpu_save(struct gic_chip_data *gic)
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{
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int i;
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u32 *ptr;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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- BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
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+ if (WARN_ON(!gic))
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+ return;
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- dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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- cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
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+ dist_base = gic_data_dist_base(gic);
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+ cpu_base = gic_data_cpu_base(gic);
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if (!dist_base || !cpu_base)
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return;
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_enable);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
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ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_active);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
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ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4);
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_conf);
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for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
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ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
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}
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-static void gic_cpu_restore(unsigned int gic_nr)
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+static void gic_cpu_restore(struct gic_chip_data *gic)
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{
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int i;
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u32 *ptr;
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void __iomem *dist_base;
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void __iomem *cpu_base;
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- BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR);
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+ if (WARN_ON(!gic))
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+ return;
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- dist_base = gic_data_dist_base(&gic_data[gic_nr]);
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- cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
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+ dist_base = gic_data_dist_base(gic);
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+ cpu_base = gic_data_cpu_base(gic);
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if (!dist_base || !cpu_base)
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return;
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_enable);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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dist_base + GIC_DIST_ENABLE_CLEAR + i * 4);
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writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
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}
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_active);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_active);
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for (i = 0; i < DIV_ROUND_UP(32, 32); i++) {
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writel_relaxed(GICD_INT_EN_CLR_X32,
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dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4);
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writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4);
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}
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- ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
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+ ptr = raw_cpu_ptr(gic->saved_ppi_conf);
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for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
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writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
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@@ -679,7 +683,7 @@ static void gic_cpu_restore(unsigned int gic_nr)
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dist_base + GIC_DIST_PRI + i * 4);
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writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
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- gic_cpu_if_up(&gic_data[gic_nr]);
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+ gic_cpu_if_up(gic);
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}
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static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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@@ -694,18 +698,18 @@ static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v)
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#endif
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switch (cmd) {
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case CPU_PM_ENTER:
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- gic_cpu_save(i);
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+ gic_cpu_save(&gic_data[i]);
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break;
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case CPU_PM_ENTER_FAILED:
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case CPU_PM_EXIT:
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- gic_cpu_restore(i);
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+ gic_cpu_restore(&gic_data[i]);
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break;
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case CPU_CLUSTER_PM_ENTER:
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- gic_dist_save(i);
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+ gic_dist_save(&gic_data[i]);
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break;
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case CPU_CLUSTER_PM_ENTER_FAILED:
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case CPU_CLUSTER_PM_EXIT:
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- gic_dist_restore(i);
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+ gic_dist_restore(&gic_data[i]);
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break;
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}
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}
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