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@@ -1189,6 +1189,12 @@ static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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+ if (trans->wowlan_d0i3) {
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+ /* Enable persistence mode to avoid reset */
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+ iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG,
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+ CSR_HW_IF_CONFIG_REG_PERSIST_MODE);
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+ }
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+
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iwl_disable_interrupts(trans);
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/*
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@@ -1207,12 +1213,14 @@ static void iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test)
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iwl_clear_bit(trans, CSR_GP_CNTRL,
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CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
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- /*
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- * reset TX queues -- some of their registers reset during S3
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- * so if we don't reset everything here the D3 image would try
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- * to execute some invalid memory upon resume
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- */
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- iwl_trans_pcie_tx_reset(trans);
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+ if (!trans->wowlan_d0i3) {
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+ /*
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+ * reset TX queues -- some of their registers reset during S3
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+ * so if we don't reset everything here the D3 image would try
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+ * to execute some invalid memory upon resume
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+ */
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+ iwl_trans_pcie_tx_reset(trans);
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+ }
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iwl_pcie_set_pwr(trans, true);
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}
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@@ -1254,12 +1262,18 @@ static int iwl_trans_pcie_d3_resume(struct iwl_trans *trans,
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iwl_pcie_set_pwr(trans, false);
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- iwl_trans_pcie_tx_reset(trans);
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+ if (trans->wowlan_d0i3) {
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+ iwl_clear_bit(trans, CSR_GP_CNTRL,
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+ CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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+ } else {
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+ iwl_trans_pcie_tx_reset(trans);
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- ret = iwl_pcie_rx_init(trans);
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- if (ret) {
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- IWL_ERR(trans, "Failed to resume the device (RX reset)\n");
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- return ret;
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+ ret = iwl_pcie_rx_init(trans);
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+ if (ret) {
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+ IWL_ERR(trans,
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+ "Failed to resume the device (RX reset)\n");
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+ return ret;
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+ }
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}
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val = iwl_read32(trans, CSR_RESET);
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