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@@ -49,6 +49,7 @@
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#include <linux/firmware.h>
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#include <linux/log2.h>
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#include <linux/aer.h>
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+#include <linux/crash_dump.h>
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#if IS_ENABLED(CONFIG_CNIC)
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#define BCM_CNIC 1
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@@ -4764,15 +4765,16 @@ bnx2_setup_msix_tbl(struct bnx2 *bp)
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BNX2_WR(bp, BNX2_PCI_GRC_WINDOW3_ADDR, BNX2_MSIX_PBA_ADDR);
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}
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-static int
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-bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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+static void
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+bnx2_wait_dma_complete(struct bnx2 *bp)
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{
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u32 val;
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- int i, rc = 0;
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- u8 old_port;
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+ int i;
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- /* Wait for the current PCI transaction to complete before
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- * issuing a reset. */
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+ /*
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+ * Wait for the current PCI transaction to complete before
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+ * issuing a reset.
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+ */
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if ((BNX2_CHIP(bp) == BNX2_CHIP_5706) ||
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(BNX2_CHIP(bp) == BNX2_CHIP_5708)) {
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BNX2_WR(bp, BNX2_MISC_ENABLE_CLR_BITS,
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@@ -4796,6 +4798,21 @@ bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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}
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}
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+ return;
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+}
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+
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+
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+static int
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+bnx2_reset_chip(struct bnx2 *bp, u32 reset_code)
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+{
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+ u32 val;
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+ int i, rc = 0;
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+ u8 old_port;
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+
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+ /* Wait for the current PCI transaction to complete before
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+ * issuing a reset. */
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+ bnx2_wait_dma_complete(bp);
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+
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/* Wait for the firmware to tell us it is ok to issue a reset. */
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bnx2_fw_sync(bp, BNX2_DRV_MSG_DATA_WAIT0 | reset_code, 1, 1);
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@@ -8580,6 +8597,15 @@ bnx2_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
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pci_set_drvdata(pdev, dev);
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+ /*
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+ * In-flight DMA from 1st kernel could continue going in kdump kernel.
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+ * New io-page table has been created before bnx2 does reset at open stage.
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+ * We have to wait for the in-flight DMA to complete to avoid it look up
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+ * into the newly created io-page table.
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+ */
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+ if (is_kdump_kernel())
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+ bnx2_wait_dma_complete(bp);
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+
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memcpy(dev->dev_addr, bp->mac_addr, ETH_ALEN);
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dev->hw_features = NETIF_F_IP_CSUM | NETIF_F_SG |
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