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@@ -21,10 +21,13 @@ Required properties:
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* "byte_clk"
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* "byte_clk"
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* "pixel_clk"
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* "pixel_clk"
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* "core_clk"
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* "core_clk"
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+ For DSIv2, we need an additional clock:
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+ * "src_clk"
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- vdd-supply: phandle to vdd regulator device node
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- vdd-supply: phandle to vdd regulator device node
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- vddio-supply: phandle to vdd-io regulator device node
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- vddio-supply: phandle to vdd-io regulator device node
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- vdda-supply: phandle to vdda regulator device node
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- vdda-supply: phandle to vdda regulator device node
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- qcom,dsi-phy: phandle to DSI PHY device node
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- qcom,dsi-phy: phandle to DSI PHY device node
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+- syscon-sfpb: A phandle to mmss_sfpb syscon node (only for DSIv2)
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Optional properties:
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Optional properties:
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- panel@0: Node of panel connected to this DSI controller.
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- panel@0: Node of panel connected to this DSI controller.
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@@ -51,6 +54,7 @@ Required properties:
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* "qcom,dsi-phy-28nm-hpm"
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* "qcom,dsi-phy-28nm-hpm"
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* "qcom,dsi-phy-28nm-lp"
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* "qcom,dsi-phy-28nm-lp"
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* "qcom,dsi-phy-20nm"
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* "qcom,dsi-phy-20nm"
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+ * "qcom,dsi-phy-28nm-8960"
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- reg: Physical base address and length of the registers of PLL, PHY and PHY
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- reg: Physical base address and length of the registers of PLL, PHY and PHY
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regulator
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regulator
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- reg-names: The names of register regions. The following regions are required:
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- reg-names: The names of register regions. The following regions are required:
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