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@@ -0,0 +1,662 @@
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+/*******************************************************************************
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+ *
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+ * Intel Ethernet Controller XL710 Family Linux Driver
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+ * Copyright(c) 2013 - 2014 Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * You should have received a copy of the GNU General Public License along
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+ * with this program. If not, see <http://www.gnu.org/licenses/>.
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+ *
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+ * The full GNU General Public License is included in this distribution in
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+ * the file called "COPYING".
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+ *
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+ * Contact Information:
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+ * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
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+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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+ *
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+ ******************************************************************************/
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+
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+#include "i40e.h"
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+#include <linux/export.h>
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+#include <linux/ptp_classify.h>
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+
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+/* The XL710 timesync is very much like Intel's 82599 design when it comes to
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+ * the fundamental clock design. However, the clock operations are much simpler
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+ * in the XL710 because the device supports a full 64 bits of nanoseconds.
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+ * Because the field is so wide, we can forgo the cycle counter and just
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+ * operate with the nanosecond field directly without fear of overflow.
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+ *
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+ * Much like the 82599, the update period is dependent upon the link speed:
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+ * At 40Gb link or no link, the period is 1.6ns.
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+ * At 10Gb link, the period is multiplied by 2. (3.2ns)
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+ * At 1Gb link, the period is multiplied by 20. (32ns)
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+ * 1588 functionality is not supported at 100Mbps.
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+ */
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+#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
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+#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
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+#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
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+
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+#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 (0x1 << \
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+ I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
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+#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (0x2 << \
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+ I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
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+#define I40E_PTP_TX_TIMEOUT (HZ * 15)
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+
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+/**
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+ * i40e_ptp_read - Read the PHC time from the device
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+ * @pf: Board private structure
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+ * @ts: timespec structure to hold the current time value
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+ *
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+ * This function reads the PRTTSYN_TIME registers and stores them in a
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+ * timespec. However, since the registers are 64 bits of nanoseconds, we must
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+ * convert the result to a timespec before we can return.
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+ **/
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+static void i40e_ptp_read(struct i40e_pf *pf, struct timespec *ts)
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+{
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+ struct i40e_hw *hw = &pf->hw;
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+ u32 hi, lo;
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+ u64 ns;
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+
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+ /* The timer latches on the lowest register read. */
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+ lo = rd32(hw, I40E_PRTTSYN_TIME_L);
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+ hi = rd32(hw, I40E_PRTTSYN_TIME_H);
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+
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+ ns = (((u64)hi) << 32) | lo;
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+
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+ *ts = ns_to_timespec(ns);
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+}
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+
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+/**
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+ * i40e_ptp_write - Write the PHC time to the device
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+ * @pf: Board private structure
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+ * @ts: timespec structure that holds the new time value
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+ *
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+ * This function writes the PRTTSYN_TIME registers with the user value. Since
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+ * we receive a timespec from the stack, we must convert that timespec into
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+ * nanoseconds before programming the registers.
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+ **/
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+static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec *ts)
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+{
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+ struct i40e_hw *hw = &pf->hw;
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+ u64 ns = timespec_to_ns(ts);
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+
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+ /* The timer will not update until the high register is written, so
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+ * write the low register first.
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+ */
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+ wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
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+ wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
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+}
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+
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+/**
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+ * i40e_ptp_convert_to_hwtstamp - Convert device clock to system time
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+ * @hwtstamps: Timestamp structure to update
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+ * @timestamp: Timestamp from the hardware
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+ *
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+ * We need to convert the NIC clock value into a hwtstamp which can be used by
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+ * the upper level timestamping functions. Since the timestamp is simply a 64-
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+ * bit nanosecond value, we can call ns_to_ktime directly to handle this.
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+ **/
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+static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
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+ u64 timestamp)
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+{
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+ memset(hwtstamps, 0, sizeof(*hwtstamps));
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+
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+ hwtstamps->hwtstamp = ns_to_ktime(timestamp);
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+}
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+
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+/**
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+ * i40e_ptp_adjfreq - Adjust the PHC frequency
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+ * @ptp: The PTP clock structure
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+ * @ppb: Parts per billion adjustment from the base
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+ *
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+ * Adjust the frequency of the PHC by the indicated parts per billion from the
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+ * base frequency.
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+ **/
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+static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
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+{
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+ struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
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+ struct i40e_hw *hw = &pf->hw;
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+ u64 adj, freq, diff;
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+ int neg_adj = 0;
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+
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+ if (ppb < 0) {
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+ neg_adj = 1;
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+ ppb = -ppb;
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+ }
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+
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+ smp_mb(); /* Force any pending update before accessing. */
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+ adj = ACCESS_ONCE(pf->ptp_base_adj);
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+
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+ freq = adj;
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+ freq *= ppb;
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+ diff = div_u64(freq, 1000000000ULL);
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+
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+ if (neg_adj)
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+ adj -= diff;
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+ else
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+ adj += diff;
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+
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+ wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
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+ wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
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+
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+ return 0;
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+}
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+
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+/**
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+ * i40e_ptp_adjtime - Adjust the PHC time
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+ * @ptp: The PTP clock structure
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+ * @delta: Offset in nanoseconds to adjust the PHC time by
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+ *
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+ * Adjust the frequency of the PHC by the indicated parts per billion from the
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+ * base frequency.
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+ **/
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+static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
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+{
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+ struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
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+ struct timespec now, then = ns_to_timespec(delta);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&pf->tmreg_lock, flags);
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+
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+ i40e_ptp_read(pf, &now);
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+ now = timespec_add(now, then);
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+ i40e_ptp_write(pf, (const struct timespec *)&now);
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+
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+ spin_unlock_irqrestore(&pf->tmreg_lock, flags);
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+
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+ return 0;
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+}
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+
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+/**
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+ * i40e_ptp_gettime - Get the time of the PHC
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+ * @ptp: The PTP clock structure
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+ * @ts: timespec structure to hold the current time value
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+ *
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+ * Read the device clock and return the correct value on ns, after converting it
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+ * into a timespec struct.
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+ **/
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+static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
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+{
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+ struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&pf->tmreg_lock, flags);
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+ i40e_ptp_read(pf, ts);
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+ spin_unlock_irqrestore(&pf->tmreg_lock, flags);
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+
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+ return 0;
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+}
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+
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+/**
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+ * i40e_ptp_settime - Set the time of the PHC
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+ * @ptp: The PTP clock structure
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+ * @ts: timespec structure that holds the new time value
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+ *
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+ * Set the device clock to the user input value. The conversion from timespec
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+ * to ns happens in the write function.
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+ **/
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+static int i40e_ptp_settime(struct ptp_clock_info *ptp,
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+ const struct timespec *ts)
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+{
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+ struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
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+ unsigned long flags;
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+
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+ spin_lock_irqsave(&pf->tmreg_lock, flags);
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+ i40e_ptp_write(pf, ts);
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+ spin_unlock_irqrestore(&pf->tmreg_lock, flags);
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+
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+ return 0;
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+}
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+
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+/**
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+ * i40e_ptp_tx_work
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+ * @work: pointer to work struct
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+ *
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+ * This work function polls the PRTTSYN_STAT_0.TXTIME bit to determine when a
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+ * Tx timestamp event has occurred, in order to pass the Tx timestamp value up
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+ * the stack in the skb.
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+ */
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+static void i40e_ptp_tx_work(struct work_struct *work)
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+{
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+ struct i40e_pf *pf = container_of(work, struct i40e_pf,
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+ ptp_tx_work);
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+ struct i40e_hw *hw = &pf->hw;
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+ u32 prttsyn_stat_0;
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+
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+ if (!pf->ptp_tx_skb)
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+ return;
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+
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+ if (time_is_before_jiffies(pf->ptp_tx_start +
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+ I40E_PTP_TX_TIMEOUT)) {
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+ dev_kfree_skb_any(pf->ptp_tx_skb);
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+ pf->ptp_tx_skb = NULL;
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+ pf->tx_hwtstamp_timeouts++;
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+ dev_warn(&pf->pdev->dev, "clearing Tx timestamp hang");
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+ return;
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+ }
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+
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+ prttsyn_stat_0 = rd32(hw, I40E_PRTTSYN_STAT_0);
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+ if (prttsyn_stat_0 & I40E_PRTTSYN_STAT_0_TXTIME_MASK)
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+ i40e_ptp_tx_hwtstamp(pf);
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+ else
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+ schedule_work(&pf->ptp_tx_work);
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+}
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+
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+/**
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+ * i40e_ptp_enable - Enable/disable ancillary features of the PHC subsystem
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+ * @ptp: The PTP clock structure
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+ * @rq: The requested feature to change
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+ * @on: Enable/disable flag
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+ *
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+ * The XL710 does not support any of the ancillary features of the PHC
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+ * subsystem, so this function may just return.
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+ **/
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+static int i40e_ptp_enable(struct ptp_clock_info *ptp,
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+ struct ptp_clock_request *rq, int on)
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+{
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+ return -EOPNOTSUPP;
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+}
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+
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+/**
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+ * i40e_ptp_rx_hang - Detect error case when Rx timestamp registers are hung
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+ * @vsi: The VSI with the rings relevant to 1588
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+ *
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+ * This watchdog task is scheduled to detect error case where hardware has
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+ * dropped an Rx packet that was timestamped when the ring is full. The
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+ * particular error is rare but leaves the device in a state unable to timestamp
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+ * any future packets.
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+ **/
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+void i40e_ptp_rx_hang(struct i40e_vsi *vsi)
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+{
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+ struct i40e_pf *pf = vsi->back;
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+ struct i40e_hw *hw = &pf->hw;
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+ struct i40e_ring *rx_ring;
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+ unsigned long rx_event;
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+ u32 prttsyn_stat;
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+ int n;
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+
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+ if (pf->flags & I40E_FLAG_PTP)
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+ return;
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+
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+ prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
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+
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+ /* Unless all four receive timestamp registers are latched, we are not
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+ * concerned about a possible PTP Rx hang, so just update the timeout
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+ * counter and exit.
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+ */
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+ if (!(prttsyn_stat & ((I40E_PRTTSYN_STAT_1_RXT0_MASK <<
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+ I40E_PRTTSYN_STAT_1_RXT0_SHIFT) |
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+ (I40E_PRTTSYN_STAT_1_RXT1_MASK <<
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+ I40E_PRTTSYN_STAT_1_RXT1_SHIFT) |
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+ (I40E_PRTTSYN_STAT_1_RXT2_MASK <<
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+ I40E_PRTTSYN_STAT_1_RXT2_SHIFT) |
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+ (I40E_PRTTSYN_STAT_1_RXT3_MASK <<
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+ I40E_PRTTSYN_STAT_1_RXT3_SHIFT)))) {
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+ pf->last_rx_ptp_check = jiffies;
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+ return;
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+ }
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+
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+ /* Determine the most recent watchdog or rx_timestamp event. */
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+ rx_event = pf->last_rx_ptp_check;
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+ for (n = 0; n < vsi->num_queue_pairs; n++) {
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+ rx_ring = vsi->rx_rings[n];
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+ if (time_after(rx_ring->last_rx_timestamp, rx_event))
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+ rx_event = rx_ring->last_rx_timestamp;
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+ }
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+
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+ /* Only need to read the high RXSTMP register to clear the lock */
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+ if (time_is_before_jiffies(rx_event + 5 * HZ)) {
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+ rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
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+ rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
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+ rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
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+ rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
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+ pf->last_rx_ptp_check = jiffies;
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+ pf->rx_hwtstamp_cleared++;
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+ dev_warn(&vsi->back->pdev->dev,
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+ "%s: clearing Rx timestamp hang",
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+ __func__);
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+ }
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+}
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+
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+/**
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+ * i40e_ptp_tx_hwtstamp - Utility function which returns the Tx timestamp
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+ * @pf: Board private structure
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+ *
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+ * Read the value of the Tx timestamp from the registers, convert it into a
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+ * value consumable by the stack, and store that result into the shhwtstamps
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+ * struct before returning it up the stack.
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+ **/
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+void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
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+{
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+ struct skb_shared_hwtstamps shhwtstamps;
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+ struct i40e_hw *hw = &pf->hw;
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+ u32 hi, lo;
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+ u64 ns;
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+
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+ lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
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+ hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
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+
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+ ns = (((u64)hi) << 32) | lo;
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+
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+ i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
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+ skb_tstamp_tx(pf->ptp_tx_skb, &shhwtstamps);
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+ dev_kfree_skb_any(pf->ptp_tx_skb);
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+ pf->ptp_tx_skb = NULL;
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+}
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+
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+/**
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+ * i40e_ptp_rx_hwtstamp - Utility function which checks for an Rx timestamp
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+ * @pf: Board private structure
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+ * @skb: Particular skb to send timestamp with
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+ * @index: Index into the receive timestamp registers for the timestamp
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+ *
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+ * The XL710 receives a notification in the receive descriptor with an offset
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+ * into the set of RXTIME registers where the timestamp is for that skb. This
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+ * function goes and fetches the receive timestamp from that offset, if a valid
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+ * one exists. The RXTIME registers are in ns, so we must convert the result
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+ * first.
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+ **/
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+void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
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+{
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+ u32 prttsyn_stat, hi, lo;
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+ struct i40e_hw *hw;
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+ u64 ns;
|
|
|
+
|
|
|
+ /* Since we cannot turn off the Rx timestamp logic if the device is
|
|
|
+ * doing Tx timestamping, check if Rx timestamping is configured.
|
|
|
+ */
|
|
|
+ if (!pf->ptp_rx)
|
|
|
+ return;
|
|
|
+
|
|
|
+ hw = &pf->hw;
|
|
|
+
|
|
|
+ prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
|
|
|
+
|
|
|
+ if (!(prttsyn_stat & (1 << index)))
|
|
|
+ return;
|
|
|
+
|
|
|
+ lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
|
|
|
+ hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
|
|
|
+
|
|
|
+ ns = (((u64)hi) << 32) | lo;
|
|
|
+
|
|
|
+ i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_ptp_set_increment - Utility function to update clock increment rate
|
|
|
+ * @pf: Board private structure
|
|
|
+ *
|
|
|
+ * During a link change, the DMA frequency that drives the 1588 logic will
|
|
|
+ * change. In order to keep the PRTTSYN_TIME registers in units of nanoseconds,
|
|
|
+ * we must update the increment value per clock tick.
|
|
|
+ **/
|
|
|
+void i40e_ptp_set_increment(struct i40e_pf *pf)
|
|
|
+{
|
|
|
+ struct i40e_link_status *hw_link_info;
|
|
|
+ struct i40e_hw *hw = &pf->hw;
|
|
|
+ u64 incval;
|
|
|
+
|
|
|
+ hw_link_info = &hw->phy.link_info;
|
|
|
+
|
|
|
+ i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
|
|
|
+
|
|
|
+ switch (hw_link_info->link_speed) {
|
|
|
+ case I40E_LINK_SPEED_10GB:
|
|
|
+ incval = I40E_PTP_10GB_INCVAL;
|
|
|
+ break;
|
|
|
+ case I40E_LINK_SPEED_1GB:
|
|
|
+ incval = I40E_PTP_1GB_INCVAL;
|
|
|
+ break;
|
|
|
+ case I40E_LINK_SPEED_100MB:
|
|
|
+ dev_warn(&pf->pdev->dev,
|
|
|
+ "%s: 1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n",
|
|
|
+ __func__);
|
|
|
+ incval = 0;
|
|
|
+ break;
|
|
|
+ case I40E_LINK_SPEED_40GB:
|
|
|
+ default:
|
|
|
+ incval = I40E_PTP_40GB_INCVAL;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Write the new increment value into the increment register. The
|
|
|
+ * hardware will not update the clock until both registers have been
|
|
|
+ * written.
|
|
|
+ */
|
|
|
+ wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
|
|
|
+ wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
|
|
|
+
|
|
|
+ /* Update the base adjustement value. */
|
|
|
+ ACCESS_ONCE(pf->ptp_base_adj) = incval;
|
|
|
+ smp_mb(); /* Force the above update. */
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_ptp_get_ts_config - ioctl interface to read the HW timestamping
|
|
|
+ * @pf: Board private structure
|
|
|
+ * @ifreq: ioctl data
|
|
|
+ *
|
|
|
+ * Obtain the current hardware timestamping settigs as requested. To do this,
|
|
|
+ * keep a shadow copy of the timestamp settings rather than attempting to
|
|
|
+ * deconstruct it from the registers.
|
|
|
+ **/
|
|
|
+int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
|
|
|
+{
|
|
|
+ struct hwtstamp_config *config = &pf->tstamp_config;
|
|
|
+
|
|
|
+ return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
|
|
|
+ -EFAULT : 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_ptp_set_ts_config - ioctl interface to control the HW timestamping
|
|
|
+ * @pf: Board private structure
|
|
|
+ * @ifreq: ioctl data
|
|
|
+ *
|
|
|
+ * Respond to the user filter requests and make the appropriate hardware
|
|
|
+ * changes here. The XL710 cannot support splitting of the Tx/Rx timestamping
|
|
|
+ * logic, so keep track in software of whether to indicate these timestamps
|
|
|
+ * or not.
|
|
|
+ *
|
|
|
+ * It is permissible to "upgrade" the user request to a broader filter, as long
|
|
|
+ * as the user receives the timestamps they care about and the user is notified
|
|
|
+ * the filter has been broadened.
|
|
|
+ **/
|
|
|
+int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
|
|
|
+{
|
|
|
+ struct i40e_hw *hw = &pf->hw;
|
|
|
+ struct hwtstamp_config *config = &pf->tstamp_config;
|
|
|
+ u32 pf_id, tsyntype, regval;
|
|
|
+
|
|
|
+ if (copy_from_user(config, ifr->ifr_data, sizeof(*config)))
|
|
|
+ return -EFAULT;
|
|
|
+
|
|
|
+ /* Reserved for future extensions. */
|
|
|
+ if (config->flags)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ /* Confirm that 1588 is supported on this PF. */
|
|
|
+ pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
|
|
|
+ I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
|
|
|
+ if (hw->pf_id != pf_id)
|
|
|
+ return -EINVAL;
|
|
|
+
|
|
|
+ switch (config->tx_type) {
|
|
|
+ case HWTSTAMP_TX_OFF:
|
|
|
+ pf->ptp_tx = false;
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_TX_ON:
|
|
|
+ pf->ptp_tx = true;
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ return -ERANGE;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (config->rx_filter) {
|
|
|
+ case HWTSTAMP_FILTER_NONE:
|
|
|
+ pf->ptp_rx = false;
|
|
|
+ tsyntype = 0;
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
|
|
|
+ pf->ptp_rx = true;
|
|
|
+ tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
|
|
|
+ I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
|
|
|
+ I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
|
|
|
+ config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
|
|
|
+ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
|
|
|
+ pf->ptp_rx = true;
|
|
|
+ tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
|
|
|
+ I40E_PRTTSYN_CTL1_TSYNTYPE_V2 |
|
|
|
+ I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
|
|
|
+ config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
|
|
|
+ break;
|
|
|
+ case HWTSTAMP_FILTER_ALL:
|
|
|
+ default:
|
|
|
+ return -ERANGE;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Clear out all 1588-related registers to clear and unlatch them. */
|
|
|
+ rd32(hw, I40E_PRTTSYN_STAT_0);
|
|
|
+ rd32(hw, I40E_PRTTSYN_TXTIME_H);
|
|
|
+ rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
|
|
|
+ rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
|
|
|
+ rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
|
|
|
+ rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
|
|
|
+
|
|
|
+ /* Enable/disable the Tx timestamp interrupt based on user input. */
|
|
|
+ regval = rd32(hw, I40E_PRTTSYN_CTL0);
|
|
|
+ if (pf->ptp_tx)
|
|
|
+ regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
|
|
|
+ else
|
|
|
+ regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
|
|
|
+ wr32(hw, I40E_PRTTSYN_CTL0, regval);
|
|
|
+
|
|
|
+ regval = rd32(hw, I40E_PFINT_ICR0_ENA);
|
|
|
+ if (pf->ptp_tx)
|
|
|
+ regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
|
|
|
+ else
|
|
|
+ regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
|
|
|
+ wr32(hw, I40E_PFINT_ICR0_ENA, regval);
|
|
|
+
|
|
|
+ /* There is no simple on/off switch for Rx. To "disable" Rx support,
|
|
|
+ * ignore any received timestamps, rather than turn off the clock.
|
|
|
+ */
|
|
|
+ if (pf->ptp_rx) {
|
|
|
+ regval = rd32(hw, I40E_PRTTSYN_CTL1);
|
|
|
+ /* clear everything but the enable bit */
|
|
|
+ regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
|
|
|
+ /* now enable bits for desired Rx timestamps */
|
|
|
+ regval |= tsyntype;
|
|
|
+ wr32(hw, I40E_PRTTSYN_CTL1, regval);
|
|
|
+ }
|
|
|
+
|
|
|
+ return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
|
|
|
+ -EFAULT : 0;
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_ptp_init - Initialize the 1588 support and register the PHC
|
|
|
+ * @pf: Board private structure
|
|
|
+ *
|
|
|
+ * This function registers the device clock as a PHC. If it is successful, it
|
|
|
+ * starts the clock in the hardware.
|
|
|
+ **/
|
|
|
+void i40e_ptp_init(struct i40e_pf *pf)
|
|
|
+{
|
|
|
+ struct i40e_hw *hw = &pf->hw;
|
|
|
+ struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
|
|
|
+
|
|
|
+ strncpy(pf->ptp_caps.name, "i40e", sizeof(pf->ptp_caps.name));
|
|
|
+ pf->ptp_caps.owner = THIS_MODULE;
|
|
|
+ pf->ptp_caps.max_adj = 999999999;
|
|
|
+ pf->ptp_caps.n_ext_ts = 0;
|
|
|
+ pf->ptp_caps.pps = 0;
|
|
|
+ pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
|
|
|
+ pf->ptp_caps.adjtime = i40e_ptp_adjtime;
|
|
|
+ pf->ptp_caps.gettime = i40e_ptp_gettime;
|
|
|
+ pf->ptp_caps.settime = i40e_ptp_settime;
|
|
|
+ pf->ptp_caps.enable = i40e_ptp_enable;
|
|
|
+
|
|
|
+ /* Attempt to register the clock before enabling the hardware. */
|
|
|
+ pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
|
|
|
+ if (IS_ERR(pf->ptp_clock)) {
|
|
|
+ pf->ptp_clock = NULL;
|
|
|
+ dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
|
|
|
+ __func__);
|
|
|
+ } else {
|
|
|
+ struct timespec ts;
|
|
|
+ u32 regval;
|
|
|
+
|
|
|
+ spin_lock_init(&pf->tmreg_lock);
|
|
|
+ INIT_WORK(&pf->ptp_tx_work, i40e_ptp_tx_work);
|
|
|
+
|
|
|
+ dev_info(&pf->pdev->dev, "%s: added PHC on %s\n", __func__,
|
|
|
+ netdev->name);
|
|
|
+ pf->flags |= I40E_FLAG_PTP;
|
|
|
+
|
|
|
+ /* Ensure the clocks are running. */
|
|
|
+ regval = rd32(hw, I40E_PRTTSYN_CTL0);
|
|
|
+ regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
|
|
|
+ wr32(hw, I40E_PRTTSYN_CTL0, regval);
|
|
|
+ regval = rd32(hw, I40E_PRTTSYN_CTL1);
|
|
|
+ regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
|
|
|
+ wr32(hw, I40E_PRTTSYN_CTL1, regval);
|
|
|
+
|
|
|
+ /* Set the increment value per clock tick. */
|
|
|
+ i40e_ptp_set_increment(pf);
|
|
|
+
|
|
|
+ /* reset the tstamp_config */
|
|
|
+ memset(&pf->tstamp_config, 0, sizeof(pf->tstamp_config));
|
|
|
+
|
|
|
+ /* Set the clock value. */
|
|
|
+ ts = ktime_to_timespec(ktime_get_real());
|
|
|
+ i40e_ptp_settime(&pf->ptp_caps, &ts);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+/**
|
|
|
+ * i40e_ptp_stop - Disable the driver/hardware support and unregister the PHC
|
|
|
+ * @pf: Board private structure
|
|
|
+ *
|
|
|
+ * This function handles the cleanup work required from the initialization by
|
|
|
+ * clearing out the important information and unregistering the PHC.
|
|
|
+ **/
|
|
|
+void i40e_ptp_stop(struct i40e_pf *pf)
|
|
|
+{
|
|
|
+ pf->flags &= ~I40E_FLAG_PTP;
|
|
|
+ pf->ptp_tx = false;
|
|
|
+ pf->ptp_rx = false;
|
|
|
+
|
|
|
+ cancel_work_sync(&pf->ptp_tx_work);
|
|
|
+ if (pf->ptp_tx_skb) {
|
|
|
+ dev_kfree_skb_any(pf->ptp_tx_skb);
|
|
|
+ pf->ptp_tx_skb = NULL;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (pf->ptp_clock) {
|
|
|
+ ptp_clock_unregister(pf->ptp_clock);
|
|
|
+ pf->ptp_clock = NULL;
|
|
|
+ dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
|
|
|
+ pf->vsi[pf->lan_vsi]->netdev->name);
|
|
|
+ }
|
|
|
+}
|
David S. Miller