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clk: rockchip: rk3288 export i2s0_clkout for use in DT

This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Sonny Rao 10 年之前
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6d288b169b
共有 2 個文件被更改,包括 2 次插入1 次删除
  1. 1 1
      drivers/clk/rockchip/clk-rk3288.c
  2. 1 0
      include/dt-bindings/clock/rk3288-cru.h

+ 1 - 1
drivers/clk/rockchip/clk-rk3288.c

@@ -308,7 +308,7 @@ static struct rockchip_clk_branch rk3288_clk_branches[] __initdata = {
 			RK3288_CLKGATE_CON(4), 2, GFLAGS),
 			RK3288_CLKGATE_CON(4), 2, GFLAGS),
 	MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 	MUX(0, "i2s_pre", mux_i2s_pre_p, CLK_SET_RATE_PARENT,
 			RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
 			RK3288_CLKSEL_CON(4), 8, 2, MFLAGS),
-	COMPOSITE_NODIV(0, "i2s0_clkout", mux_i2s_clkout_p, 0,
+	COMPOSITE_NODIV(SCLK_I2S0_OUT, "i2s0_clkout", mux_i2s_clkout_p, 0,
 			RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 			RK3288_CLKSEL_CON(4), 12, 1, MFLAGS,
 			RK3288_CLKGATE_CON(4), 0, GFLAGS),
 			RK3288_CLKGATE_CON(4), 0, GFLAGS),
 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,
 	GATE(SCLK_I2S0, "sclk_i2s0", "i2s_pre", CLK_SET_RATE_PARENT,

+ 1 - 0
include/dt-bindings/clock/rk3288-cru.h

@@ -71,6 +71,7 @@
 #define SCLK_HDMI_CEC		110
 #define SCLK_HDMI_CEC		110
 #define SCLK_HEVC_CABAC		111
 #define SCLK_HEVC_CABAC		111
 #define SCLK_HEVC_CORE		112
 #define SCLK_HEVC_CORE		112
+#define SCLK_I2S0_OUT		113
 
 
 #define DCLK_VOP0		190
 #define DCLK_VOP0		190
 #define DCLK_VOP1		191
 #define DCLK_VOP1		191