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@@ -316,9 +316,9 @@ static void exynos_pcie_assert_reset(struct pcie_port *pp)
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static int exynos_pcie_establish_link(struct pcie_port *pp)
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{
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- u32 val;
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- int count = 0;
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp);
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+ u32 val;
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+ unsigned int retries;
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if (dw_pcie_link_up(pp)) {
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dev_err(pp->dev, "Link already up\n");
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@@ -357,27 +357,23 @@ static int exynos_pcie_establish_link(struct pcie_port *pp)
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PCIE_APP_LTSSM_ENABLE);
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/* check if the link is up or not */
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- while (!dw_pcie_link_up(pp)) {
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- mdelay(100);
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- count++;
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- if (count == 10) {
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- while (exynos_phy_readl(exynos_pcie,
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- PCIE_PHY_PLL_LOCKED) == 0) {
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- val = exynos_blk_readl(exynos_pcie,
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- PCIE_PHY_PLL_LOCKED);
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- dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
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- }
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- /* power off phy */
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- exynos_pcie_power_off_phy(pp);
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-
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- dev_err(pp->dev, "PCIe Link Fail\n");
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- return -EINVAL;
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+ for (retries = 0; retries < 10; retries++) {
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+ if (dw_pcie_link_up(pp)) {
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+ dev_info(pp->dev, "Link up\n");
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+ return 0;
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}
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+ mdelay(100);
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}
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- dev_info(pp->dev, "Link up\n");
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+ while (exynos_phy_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED) == 0) {
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+ val = exynos_blk_readl(exynos_pcie, PCIE_PHY_PLL_LOCKED);
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+ dev_info(pp->dev, "PLL Locked: 0x%x\n", val);
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+ }
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+ /* power off phy */
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+ exynos_pcie_power_off_phy(pp);
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- return 0;
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+ dev_err(pp->dev, "PCIe Link Fail\n");
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+ return -EINVAL;
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}
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static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp)
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