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@@ -68,5 +68,8 @@
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#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_B_CLK0 59
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#define CLKID_SD_EMMC_C_CLK0 60
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#define CLKID_SD_EMMC_C_CLK0 60
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#define CLKID_HIFI_PLL 69
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#define CLKID_HIFI_PLL 69
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+#define CLKID_PCIE_CML_EN0 79
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+#define CLKID_PCIE_CML_EN1 80
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+#define CLKID_MIPI_ENABLE 81
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#endif /* __AXG_CLKC_H */
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#endif /* __AXG_CLKC_H */
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