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@@ -2141,6 +2141,21 @@ static void intel_ddi_clk_select(struct intel_encoder *encoder,
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}
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}
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+static void intel_ddi_clk_disable(struct intel_encoder *encoder)
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+{
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+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
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+ enum port port = intel_ddi_get_encoder_port(encoder);
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+
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+ if (IS_CANNONLAKE(dev_priv))
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+ I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
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+ DPCLKA_CFGCR0_DDI_CLK_OFF(port));
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+ else if (IS_GEN9_BC(dev_priv))
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+ I915_WRITE(DPLL_CTRL2, I915_READ(DPLL_CTRL2) |
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+ DPLL_CTRL2_DDI_CLK_OFF(port));
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+ else if (INTEL_GEN(dev_priv) < 9)
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+ I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
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+}
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+
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static void intel_ddi_pre_enable_dp(struct intel_encoder *encoder,
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int link_rate, uint32_t lane_count,
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struct intel_shared_dpll *pll,
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@@ -2301,14 +2316,7 @@ static void intel_ddi_post_disable(struct intel_encoder *intel_encoder,
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if (dig_port)
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intel_display_power_put(dev_priv, dig_port->ddi_io_power_domain);
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- if (IS_CANNONLAKE(dev_priv))
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- I915_WRITE(DPCLKA_CFGCR0, I915_READ(DPCLKA_CFGCR0) |
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- DPCLKA_CFGCR0_DDI_CLK_OFF(port));
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- else if (IS_GEN9_BC(dev_priv))
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- I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
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- DPLL_CTRL2_DDI_CLK_OFF(port)));
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- else if (INTEL_GEN(dev_priv) < 9)
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- I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
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+ intel_ddi_clk_disable(intel_encoder);
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if (type == INTEL_OUTPUT_HDMI) {
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struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
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