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@@ -23,6 +23,9 @@
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static DEFINE_SPINLOCK(clk_lock);
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static DEFINE_SPINLOCK(clk_lock);
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+/* Maximum number of parents our clocks have */
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+#define SUNXI_MAX_PARENTS 5
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+
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/**
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/**
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* sun4i_osc_clk_setup() - Setup function for gatable oscillator
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* sun4i_osc_clk_setup() - Setup function for gatable oscillator
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*/
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*/
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@@ -214,6 +217,40 @@ static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
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}
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}
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}
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}
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+/**
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+ * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
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+ * PLL5 rate is calculated as follows
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+ * rate = parent_rate * n * (k + 1)
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+ * parent_rate is always 24Mhz
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+ */
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+
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+static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div;
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+
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+ /* Normalize value to a parent_rate multiple (24M) */
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+ div = *freq / parent_rate;
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+ *freq = parent_rate * div;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ if (div < 31)
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+ *k = 0;
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+ else if (div / 2 < 31)
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+ *k = 1;
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+ else if (div / 3 < 31)
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+ *k = 2;
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+ else
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+ *k = 3;
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+
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+ *n = DIV_ROUND_UP(div, (*k+1));
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+}
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+
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+
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+
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/**
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/**
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* sun4i_get_apb1_factors() - calculates m, p factors for APB1
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* APB1 rate is calculated as follows
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* APB1 rate is calculated as follows
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@@ -257,11 +294,97 @@ static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
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+/**
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+ * sun4i_get_mod0_factors() - calculates m, n factors for MOD0-style clocks
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+ * MMC rate is calculated as follows
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+ * rate = (parent_rate >> p) / (m + 1);
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+ */
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+
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+static void sun4i_get_mod0_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div, calcm, calcp;
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+
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+ /* These clocks can only divide, so we will never be able to achieve
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+ * frequencies higher than the parent frequency */
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+ if (*freq > parent_rate)
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+ *freq = parent_rate;
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+
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+ div = parent_rate / *freq;
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+
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+ if (div < 16)
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+ calcp = 0;
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+ else if (div / 2 < 16)
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+ calcp = 1;
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+ else if (div / 4 < 16)
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+ calcp = 2;
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+ else
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+ calcp = 3;
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+
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+ calcm = DIV_ROUND_UP(div, 1 << calcp);
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+
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+ *freq = (parent_rate >> calcp) / calcm;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *m = calcm - 1;
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+ *p = calcp;
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+}
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+
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+
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+
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+/**
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+ * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
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+ * CLK_OUT rate is calculated as follows
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+ * rate = (parent_rate >> p) / (m + 1);
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+ */
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+
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+static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
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+ u8 *n, u8 *k, u8 *m, u8 *p)
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+{
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+ u8 div, calcm, calcp;
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+
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+ /* These clocks can only divide, so we will never be able to achieve
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+ * frequencies higher than the parent frequency */
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+ if (*freq > parent_rate)
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+ *freq = parent_rate;
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+
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+ div = parent_rate / *freq;
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+
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+ if (div < 32)
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+ calcp = 0;
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+ else if (div / 2 < 32)
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+ calcp = 1;
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+ else if (div / 4 < 32)
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+ calcp = 2;
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+ else
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+ calcp = 3;
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+
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+ calcm = DIV_ROUND_UP(div, 1 << calcp);
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+
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+ *freq = (parent_rate >> calcp) / calcm;
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+
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+ /* we were called to round the frequency, we can now return */
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+ if (n == NULL)
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+ return;
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+
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+ *m = calcm - 1;
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+ *p = calcp;
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+}
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+
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+
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+
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/**
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/**
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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* sunxi_factors_clk_setup() - Setup function for factor clocks
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*/
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*/
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+#define SUNXI_FACTORS_MUX_MASK 0x3
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+
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struct factors_data {
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struct factors_data {
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+ int enable;
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+ int mux;
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struct clk_factors_config *table;
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struct clk_factors_config *table;
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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void (*getter) (u32 *rate, u32 parent_rate, u8 *n, u8 *k, u8 *m, u8 *p);
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};
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};
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@@ -286,6 +409,13 @@ static struct clk_factors_config sun6i_a31_pll1_config = {
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.mwidth = 2,
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.mwidth = 2,
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};
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};
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+static struct clk_factors_config sun4i_pll5_config = {
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+ .nshift = 8,
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+ .nwidth = 5,
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+ .kshift = 4,
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+ .kwidth = 2,
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+};
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+
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static struct clk_factors_config sun4i_apb1_config = {
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static struct clk_factors_config sun4i_apb1_config = {
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.mshift = 0,
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.mshift = 0,
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.mwidth = 5,
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.mwidth = 5,
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@@ -293,40 +423,143 @@ static struct clk_factors_config sun4i_apb1_config = {
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.pwidth = 2,
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.pwidth = 2,
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};
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};
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+/* user manual says "n" but it's really "p" */
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+static struct clk_factors_config sun4i_mod0_config = {
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+ .mshift = 0,
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+ .mwidth = 4,
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+ .pshift = 16,
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+ .pwidth = 2,
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+};
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+
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+/* user manual says "n" but it's really "p" */
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+static struct clk_factors_config sun7i_a20_out_config = {
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+ .mshift = 8,
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+ .mwidth = 5,
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+ .pshift = 20,
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+ .pwidth = 2,
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+};
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+
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static const struct factors_data sun4i_pll1_data __initconst = {
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static const struct factors_data sun4i_pll1_data __initconst = {
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+ .enable = 31,
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.table = &sun4i_pll1_config,
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.table = &sun4i_pll1_config,
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.getter = sun4i_get_pll1_factors,
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.getter = sun4i_get_pll1_factors,
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};
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};
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static const struct factors_data sun6i_a31_pll1_data __initconst = {
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static const struct factors_data sun6i_a31_pll1_data __initconst = {
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+ .enable = 31,
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.table = &sun6i_a31_pll1_config,
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.table = &sun6i_a31_pll1_config,
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.getter = sun6i_a31_get_pll1_factors,
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.getter = sun6i_a31_get_pll1_factors,
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};
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};
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+static const struct factors_data sun4i_pll5_data __initconst = {
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+ .enable = 31,
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+ .table = &sun4i_pll5_config,
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+ .getter = sun4i_get_pll5_factors,
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+};
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+
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static const struct factors_data sun4i_apb1_data __initconst = {
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static const struct factors_data sun4i_apb1_data __initconst = {
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.table = &sun4i_apb1_config,
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.table = &sun4i_apb1_config,
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.getter = sun4i_get_apb1_factors,
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.getter = sun4i_get_apb1_factors,
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};
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};
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-static void __init sunxi_factors_clk_setup(struct device_node *node,
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- struct factors_data *data)
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+static const struct factors_data sun4i_mod0_data __initconst = {
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+ .enable = 31,
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+ .mux = 24,
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+ .table = &sun4i_mod0_config,
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+ .getter = sun4i_get_mod0_factors,
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+};
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+
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+static const struct factors_data sun7i_a20_out_data __initconst = {
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+ .enable = 31,
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+ .mux = 24,
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+ .table = &sun7i_a20_out_config,
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+ .getter = sun7i_a20_get_out_factors,
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+};
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+
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+static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
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+ const struct factors_data *data)
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{
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{
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struct clk *clk;
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struct clk *clk;
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+ struct clk_factors *factors;
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+ struct clk_gate *gate = NULL;
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+ struct clk_mux *mux = NULL;
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+ struct clk_hw *gate_hw = NULL;
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+ struct clk_hw *mux_hw = NULL;
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const char *clk_name = node->name;
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const char *clk_name = node->name;
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- const char *parent;
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+ const char *parents[SUNXI_MAX_PARENTS];
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void *reg;
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void *reg;
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+ int i = 0;
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reg = of_iomap(node, 0);
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reg = of_iomap(node, 0);
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- parent = of_clk_get_parent_name(node, 0);
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+ /* if we have a mux, we will have >1 parents */
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+ while (i < SUNXI_MAX_PARENTS &&
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+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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+ i++;
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- clk = clk_register_factors(NULL, clk_name, parent, 0, reg,
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- data->table, data->getter, &clk_lock);
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+ /* Nodes should be providing the name via clock-output-names
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+ * but originally our dts didn't, and so we used node->name.
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+ * The new, better nodes look like clk@deadbeef, so we pull the
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+ * name just in this case */
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+ if (!strcmp("clk", clk_name)) {
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+ of_property_read_string_index(node, "clock-output-names",
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+ 0, &clk_name);
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+ }
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+
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+ factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
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+ if (!factors)
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+ return NULL;
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+
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+ /* Add a gate if this factor clock can be gated */
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+ if (data->enable) {
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+ gate = kzalloc(sizeof(struct clk_gate), GFP_KERNEL);
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+ if (!gate) {
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+ kfree(factors);
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+ return NULL;
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+ }
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+
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+ /* set up gate properties */
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+ gate->reg = reg;
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+ gate->bit_idx = data->enable;
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+ gate->lock = &clk_lock;
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+ gate_hw = &gate->hw;
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+ }
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+
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+ /* Add a mux if this factor clock can be muxed */
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+ if (data->mux) {
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+ mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
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+ if (!mux) {
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+ kfree(factors);
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+ kfree(gate);
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+ return NULL;
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+ }
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+
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+ /* set up gate properties */
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+ mux->reg = reg;
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+ mux->shift = data->mux;
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+ mux->mask = SUNXI_FACTORS_MUX_MASK;
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+ mux->lock = &clk_lock;
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+ mux_hw = &mux->hw;
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+ }
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+
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+ /* set up factors properties */
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+ factors->reg = reg;
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+ factors->config = data->table;
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+ factors->get_factors = data->getter;
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+ factors->lock = &clk_lock;
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+
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+ clk = clk_register_composite(NULL, clk_name,
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+ parents, i,
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+ mux_hw, &clk_mux_ops,
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+ &factors->hw, &clk_factors_ops,
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+ gate_hw, &clk_gate_ops, 0);
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if (!IS_ERR(clk)) {
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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clk_register_clkdev(clk, clk_name, NULL);
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clk_register_clkdev(clk, clk_name, NULL);
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}
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}
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+
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+ return clk;
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}
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}
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@@ -358,13 +591,14 @@ static void __init sunxi_mux_clk_setup(struct device_node *node,
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{
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{
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struct clk *clk;
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struct clk *clk;
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const char *clk_name = node->name;
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const char *clk_name = node->name;
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- const char *parents[5];
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+ const char *parents[SUNXI_MAX_PARENTS];
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void *reg;
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void *reg;
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int i = 0;
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int i = 0;
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reg = of_iomap(node, 0);
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reg = of_iomap(node, 0);
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- while (i < 5 && (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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+ while (i < SUNXI_MAX_PARENTS &&
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+ (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
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i++;
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i++;
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clk = clk_register_mux(NULL, clk_name, parents, i,
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clk = clk_register_mux(NULL, clk_name, parents, i,
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@@ -561,11 +795,186 @@ static void __init sunxi_gates_clk_setup(struct device_node *node,
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
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}
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}
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+
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+
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+/**
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+ * sunxi_divs_clk_setup() helper data
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+ */
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+
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+#define SUNXI_DIVS_MAX_QTY 2
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+#define SUNXI_DIVISOR_WIDTH 2
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+
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+struct divs_data {
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+ const struct factors_data *factors; /* data for the factor clock */
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+ struct {
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+ u8 fixed; /* is it a fixed divisor? if not... */
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+ struct clk_div_table *table; /* is it a table based divisor? */
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+ u8 shift; /* otherwise it's a normal divisor with this shift */
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+ u8 pow; /* is it power-of-two based? */
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+ u8 gate; /* is it independently gateable? */
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+ } div[SUNXI_DIVS_MAX_QTY];
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+};
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+
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+static struct clk_div_table pll6_sata_tbl[] = {
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+ { .val = 0, .div = 6, },
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+ { .val = 1, .div = 12, },
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+ { .val = 2, .div = 18, },
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+ { .val = 3, .div = 24, },
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+ { } /* sentinel */
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+};
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+
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+static const struct divs_data pll5_divs_data __initconst = {
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+ .factors = &sun4i_pll5_data,
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+ .div = {
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+ { .shift = 0, .pow = 0, }, /* M, DDR */
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+ { .shift = 16, .pow = 1, }, /* P, other */
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+ }
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+};
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+
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+static const struct divs_data pll6_divs_data __initconst = {
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+ .factors = &sun4i_pll5_data,
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+ .div = {
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+ { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
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+ { .fixed = 2 }, /* P, other */
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+ }
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+};
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+
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+/**
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+ * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
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+ *
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+ * These clocks look something like this
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+ * ________________________
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+ * | ___divisor 1---|----> to consumer
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+ * parent >--| pll___/___divisor 2---|----> to consumer
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+ * | \_______________|____> to consumer
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+ * |________________________|
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+ */
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+
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+static void __init sunxi_divs_clk_setup(struct device_node *node,
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+ struct divs_data *data)
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+{
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+ struct clk_onecell_data *clk_data;
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+ const char *parent = node->name;
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+ const char *clk_name;
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+ struct clk **clks, *pclk;
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+ struct clk_hw *gate_hw, *rate_hw;
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+ const struct clk_ops *rate_ops;
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+ struct clk_gate *gate = NULL;
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+ struct clk_fixed_factor *fix_factor;
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+ struct clk_divider *divider;
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+ void *reg;
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+ int i = 0;
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+ int flags, clkflags;
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+
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+ /* Set up factor clock that we will be dividing */
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+ pclk = sunxi_factors_clk_setup(node, data->factors);
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+
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+ reg = of_iomap(node, 0);
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+
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+ clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
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+ if (!clk_data)
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+ return;
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+
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+ clks = kzalloc(SUNXI_DIVS_MAX_QTY * sizeof(struct clk *), GFP_KERNEL);
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+ if (!clks)
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+ goto free_clkdata;
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+
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+ clk_data->clks = clks;
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+
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+ /* It's not a good idea to have automatic reparenting changing
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+ * our RAM clock! */
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+ clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
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+
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+ for (i = 0; i < SUNXI_DIVS_MAX_QTY; i++) {
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+ if (of_property_read_string_index(node, "clock-output-names",
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+ i, &clk_name) != 0)
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+ break;
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+
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+ gate_hw = NULL;
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+ rate_hw = NULL;
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+ rate_ops = NULL;
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+
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+ /* If this leaf clock can be gated, create a gate */
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+ if (data->div[i].gate) {
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+ gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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+ if (!gate)
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+ goto free_clks;
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+
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+ gate->reg = reg;
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+ gate->bit_idx = data->div[i].gate;
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+ gate->lock = &clk_lock;
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+
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+ gate_hw = &gate->hw;
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+ }
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+
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+ /* Leaves can be fixed or configurable divisors */
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+ if (data->div[i].fixed) {
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|
+ fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
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+ if (!fix_factor)
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+ goto free_gate;
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+
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+ fix_factor->mult = 1;
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|
+ fix_factor->div = data->div[i].fixed;
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+
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+ rate_hw = &fix_factor->hw;
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|
+ rate_ops = &clk_fixed_factor_ops;
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+ } else {
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|
|
+ divider = kzalloc(sizeof(*divider), GFP_KERNEL);
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|
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+ if (!divider)
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|
+ goto free_gate;
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+
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|
|
+ flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
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+
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+ divider->reg = reg;
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|
|
+ divider->shift = data->div[i].shift;
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|
|
+ divider->width = SUNXI_DIVISOR_WIDTH;
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|
|
+ divider->flags = flags;
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|
|
|
+ divider->lock = &clk_lock;
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|
|
+ divider->table = data->div[i].table;
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|
|
+
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|
|
+ rate_hw = ÷r->hw;
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|
|
+ rate_ops = &clk_divider_ops;
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|
|
+ }
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|
+
|
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|
|
+ /* Wrap the (potential) gate and the divisor on a composite
|
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|
|
+ * clock to unify them */
|
|
|
|
+ clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
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|
|
|
+ NULL, NULL,
|
|
|
|
+ rate_hw, rate_ops,
|
|
|
|
+ gate_hw, &clk_gate_ops,
|
|
|
|
+ clkflags);
|
|
|
|
+
|
|
|
|
+ WARN_ON(IS_ERR(clk_data->clks[i]));
|
|
|
|
+ clk_register_clkdev(clks[i], clk_name, NULL);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ /* The last clock available on the getter is the parent */
|
|
|
|
+ clks[i++] = pclk;
|
|
|
|
+
|
|
|
|
+ /* Adjust to the real max */
|
|
|
|
+ clk_data->clk_num = i;
|
|
|
|
+
|
|
|
|
+ of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
|
|
|
|
+
|
|
|
|
+ return;
|
|
|
|
+
|
|
|
|
+free_gate:
|
|
|
|
+ kfree(gate);
|
|
|
|
+free_clks:
|
|
|
|
+ kfree(clks);
|
|
|
|
+free_clkdata:
|
|
|
|
+ kfree(clk_data);
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+
|
|
|
|
+
|
|
/* Matches for factors clocks */
|
|
/* Matches for factors clocks */
|
|
static const struct of_device_id clk_factors_match[] __initconst = {
|
|
static const struct of_device_id clk_factors_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
|
|
{.compatible = "allwinner,sun4i-pll1-clk", .data = &sun4i_pll1_data,},
|
|
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
|
|
{.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
|
|
{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
|
|
{.compatible = "allwinner,sun4i-apb1-clk", .data = &sun4i_apb1_data,},
|
|
|
|
+ {.compatible = "allwinner,sun4i-mod0-clk", .data = &sun4i_mod0_data,},
|
|
|
|
+ {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
|
|
{}
|
|
{}
|
|
};
|
|
};
|
|
|
|
|
|
@@ -578,6 +987,13 @@ static const struct of_device_id clk_div_match[] __initconst = {
|
|
{}
|
|
{}
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+/* Matches for divided outputs */
|
|
|
|
+static const struct of_device_id clk_divs_match[] __initconst = {
|
|
|
|
+ {.compatible = "allwinner,sun4i-pll5-clk", .data = &pll5_divs_data,},
|
|
|
|
+ {.compatible = "allwinner,sun4i-pll6-clk", .data = &pll6_divs_data,},
|
|
|
|
+ {}
|
|
|
|
+};
|
|
|
|
+
|
|
/* Matches for mux clocks */
|
|
/* Matches for mux clocks */
|
|
static const struct of_device_id clk_mux_match[] __initconst = {
|
|
static const struct of_device_id clk_mux_match[] __initconst = {
|
|
{.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
|
|
{.compatible = "allwinner,sun4i-cpu-clk", .data = &sun4i_cpu_mux_data,},
|
|
@@ -655,6 +1071,9 @@ static void __init sunxi_init_clocks(void)
|
|
/* Register divider clocks */
|
|
/* Register divider clocks */
|
|
of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
|
|
of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
|
|
|
|
|
|
|
|
+ /* Register divided output clocks */
|
|
|
|
+ of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
|
|
|
|
+
|
|
/* Register mux clocks */
|
|
/* Register mux clocks */
|
|
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
|
|
of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
|
|
|
|
|