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@@ -0,0 +1,141 @@
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+#include <linux/pci-ecam.h>
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+#include <linux/delay.h>
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+#include <linux/of.h>
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+
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+#define SMP8759_MUX 0x48
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+#define SMP8759_TEST_OUT 0x74
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+
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+struct tango_pcie {
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+ void __iomem *base;
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+};
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+
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+static int smp8759_config_read(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 *val)
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+{
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+ struct pci_config_window *cfg = bus->sysdata;
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+ struct tango_pcie *pcie = dev_get_drvdata(cfg->parent);
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+ int ret;
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+
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+ /* Reads in configuration space outside devfn 0 return garbage */
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+ if (devfn != 0)
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+ return PCIBIOS_FUNC_NOT_SUPPORTED;
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+
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+ /*
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+ * PCI config and MMIO accesses are muxed. Linux doesn't have a
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+ * mutual exclusion mechanism for config vs. MMIO accesses, so
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+ * concurrent accesses may cause corruption.
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+ */
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+ writel_relaxed(1, pcie->base + SMP8759_MUX);
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+ ret = pci_generic_config_read(bus, devfn, where, size, val);
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+ writel_relaxed(0, pcie->base + SMP8759_MUX);
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+
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+ return ret;
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+}
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+
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+static int smp8759_config_write(struct pci_bus *bus, unsigned int devfn,
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+ int where, int size, u32 val)
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+{
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+ struct pci_config_window *cfg = bus->sysdata;
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+ struct tango_pcie *pcie = dev_get_drvdata(cfg->parent);
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+ int ret;
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+
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+ writel_relaxed(1, pcie->base + SMP8759_MUX);
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+ ret = pci_generic_config_write(bus, devfn, where, size, val);
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+ writel_relaxed(0, pcie->base + SMP8759_MUX);
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+
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+ return ret;
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+}
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+
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+static struct pci_ecam_ops smp8759_ecam_ops = {
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+ .bus_shift = 20,
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+ .pci_ops = {
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+ .map_bus = pci_ecam_map_bus,
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+ .read = smp8759_config_read,
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+ .write = smp8759_config_write,
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+ }
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+};
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+
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+static int tango_pcie_link_up(struct tango_pcie *pcie)
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+{
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+ void __iomem *test_out = pcie->base + SMP8759_TEST_OUT;
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+ int i;
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+
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+ writel_relaxed(16, test_out);
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+ for (i = 0; i < 10; ++i) {
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+ u32 ltssm_state = readl_relaxed(test_out) >> 8;
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+ if ((ltssm_state & 0x1f) == 0xf) /* L0 */
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+ return 1;
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+ usleep_range(3000, 4000);
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+ }
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+
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+ return 0;
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+}
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+
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+static int tango_pcie_probe(struct platform_device *pdev)
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+{
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+ struct device *dev = &pdev->dev;
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+ struct tango_pcie *pcie;
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+ struct resource *res;
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+ int ret;
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+
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+ dev_warn(dev, "simultaneous PCI config and MMIO accesses may cause data corruption\n");
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+ add_taint(TAINT_CRAP, LOCKDEP_STILL_OK);
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+
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+ pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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+ if (!pcie)
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+ return -ENOMEM;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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+ pcie->base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(pcie->base))
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+ return PTR_ERR(pcie->base);
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+
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+ platform_set_drvdata(pdev, pcie);
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+
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+ if (!tango_pcie_link_up(pcie))
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+ return -ENODEV;
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+
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+ return pci_host_common_probe(pdev, &smp8759_ecam_ops);
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+}
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+
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+static const struct of_device_id tango_pcie_ids[] = {
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+ { .compatible = "sigma,smp8759-pcie" },
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+ { },
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+};
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+
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+static struct platform_driver tango_pcie_driver = {
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+ .probe = tango_pcie_probe,
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+ .driver = {
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+ .name = KBUILD_MODNAME,
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+ .of_match_table = tango_pcie_ids,
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+ .suppress_bind_attrs = true,
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+ },
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+};
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+builtin_platform_driver(tango_pcie_driver);
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+
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+/*
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+ * The root complex advertises the wrong device class.
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+ * Header Type 1 is for PCI-to-PCI bridges.
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+ */
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+static void tango_fixup_class(struct pci_dev *dev)
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+{
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+ dev->class = PCI_CLASS_BRIDGE_PCI << 8;
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0024, tango_fixup_class);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0028, tango_fixup_class);
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+
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+/*
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+ * The root complex exposes a "fake" BAR, which is used to filter
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+ * bus-to-system accesses. Only accesses within the range defined by this
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+ * BAR are forwarded to the host, others are ignored.
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+ *
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+ * By default, the DMA framework expects an identity mapping, and DRAM0 is
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+ * mapped at 0x80000000.
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+ */
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+static void tango_fixup_bar(struct pci_dev *dev)
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+{
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+ dev->non_compliant_bars = true;
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+ pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, 0x80000000);
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+}
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0024, tango_fixup_bar);
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+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SIGMA, 0x0028, tango_fixup_bar);
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