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@@ -129,6 +129,8 @@
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#define CSR_UCODE_DRV_GP1_CLR (CSR_BASE+0x05c)
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#define CSR_UCODE_DRV_GP2 (CSR_BASE+0x060)
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+#define CSR_MBOX_SET_REG (CSR_BASE + 0x88)
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+
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#define CSR_LED_REG (CSR_BASE+0x094)
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#define CSR_DRAM_INT_TBL_REG (CSR_BASE+0x0A0)
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#define CSR_MAC_SHADOW_REG_CTRL (CSR_BASE+0x0A8) /* 6000 and up */
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@@ -184,6 +186,8 @@
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#define CSR_HW_IF_CONFIG_REG_PREPARE (0x08000000) /* WAKE_ME */
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#define CSR_HW_IF_CONFIG_REG_PERSIST_MODE (0x40000000) /* PERSISTENCE */
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+#define CSR_MBOX_SET_REG_OS_ALIVE BIT(5)
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+
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#define CSR_INT_PERIODIC_DIS (0x00) /* disable periodic int*/
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#define CSR_INT_PERIODIC_ENA (0xFF) /* 255*32 usec ~ 8 msec*/
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