|
@@ -992,10 +992,6 @@ static void amdgpu_vm_cpu_set_ptes(struct amdgpu_pte_update_params *params,
|
|
|
i, value, flags);
|
|
|
addr += incr;
|
|
|
}
|
|
|
-
|
|
|
- /* Flush HDP */
|
|
|
- mb();
|
|
|
- amdgpu_gart_flush_gpu_tlb(params->adev, 0);
|
|
|
}
|
|
|
|
|
|
static int amdgpu_vm_wait_pd(struct amdgpu_device *adev, struct amdgpu_vm *vm,
|
|
@@ -1238,6 +1234,12 @@ int amdgpu_vm_update_directories(struct amdgpu_device *adev,
|
|
|
if (r)
|
|
|
amdgpu_vm_invalidate_level(&vm->root);
|
|
|
|
|
|
+ if (vm->use_cpu_for_update) {
|
|
|
+ /* Flush HDP */
|
|
|
+ mb();
|
|
|
+ amdgpu_gart_flush_gpu_tlb(adev, 0);
|
|
|
+ }
|
|
|
+
|
|
|
return r;
|
|
|
}
|
|
|
|
|
@@ -1745,6 +1747,12 @@ int amdgpu_vm_bo_update(struct amdgpu_device *adev,
|
|
|
list_add(&bo_va->vm_status, &vm->cleared);
|
|
|
spin_unlock(&vm->status_lock);
|
|
|
|
|
|
+ if (vm->use_cpu_for_update) {
|
|
|
+ /* Flush HDP */
|
|
|
+ mb();
|
|
|
+ amdgpu_gart_flush_gpu_tlb(adev, 0);
|
|
|
+ }
|
|
|
+
|
|
|
return 0;
|
|
|
}
|
|
|
|