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@@ -3349,33 +3349,24 @@ void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
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unsigned int pipe_mask)
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unsigned int pipe_mask)
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{
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{
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uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
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uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
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+ enum pipe pipe;
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spin_lock_irq(&dev_priv->irq_lock);
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spin_lock_irq(&dev_priv->irq_lock);
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- if (pipe_mask & 1 << PIPE_A)
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- GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
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- dev_priv->de_irq_mask[PIPE_A],
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- ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
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- if (pipe_mask & 1 << PIPE_B)
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- GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
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- dev_priv->de_irq_mask[PIPE_B],
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- ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
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- if (pipe_mask & 1 << PIPE_C)
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- GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
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- dev_priv->de_irq_mask[PIPE_C],
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- ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
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+ for_each_pipe_masked(dev_priv, pipe, pipe_mask)
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+ GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
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+ dev_priv->de_irq_mask[pipe],
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+ ~dev_priv->de_irq_mask[pipe] | extra_ier);
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spin_unlock_irq(&dev_priv->irq_lock);
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spin_unlock_irq(&dev_priv->irq_lock);
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}
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}
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void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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void gen8_irq_power_well_pre_disable(struct drm_i915_private *dev_priv,
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unsigned int pipe_mask)
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unsigned int pipe_mask)
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{
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{
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+ enum pipe pipe;
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+
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spin_lock_irq(&dev_priv->irq_lock);
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spin_lock_irq(&dev_priv->irq_lock);
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- if (pipe_mask & 1 << PIPE_A)
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- GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_A);
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- if (pipe_mask & 1 << PIPE_B)
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- GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_B);
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- if (pipe_mask & 1 << PIPE_C)
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- GEN8_IRQ_RESET_NDX(DE_PIPE, PIPE_C);
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+ for_each_pipe_masked(dev_priv, pipe, pipe_mask)
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+ GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
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spin_unlock_irq(&dev_priv->irq_lock);
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spin_unlock_irq(&dev_priv->irq_lock);
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/* make sure we're done processing display irqs */
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/* make sure we're done processing display irqs */
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