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@@ -34,6 +34,7 @@
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#include "iwl-csr.h"
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#include "iwl-prph.h"
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#include "iwl-io.h"
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+#include "iwl-scd.h"
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#include "iwl-op-mode.h"
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#include "internal.h"
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/* FIXME: need to abstract out TX command (once we know what it looks like) */
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@@ -644,17 +645,6 @@ static void iwl_pcie_txq_free(struct iwl_trans *trans, int txq_id)
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memset(txq, 0, sizeof(*txq));
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}
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-/*
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- * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
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- */
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-static void iwl_pcie_txq_set_sched(struct iwl_trans *trans, u32 mask)
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-{
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- struct iwl_trans_pcie __maybe_unused *trans_pcie =
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- IWL_TRANS_GET_PCIE_TRANS(trans);
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-
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- iwl_write_prph(trans, SCD_TXFACT, mask);
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-}
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-
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void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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{
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struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans);
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@@ -692,7 +682,7 @@ void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr)
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trans_pcie->cmd_fifo);
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/* Activate all Tx DMA/FIFO channels */
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- iwl_pcie_txq_set_sched(trans, IWL_MASK(0, 7));
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+ iwl_scd_activate_fifos(trans);
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/* Enable DMA channel */
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for (chan = 0; chan < FH_TCSR_CHNL_NUM; chan++)
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@@ -745,7 +735,7 @@ int iwl_pcie_tx_stop(struct iwl_trans *trans)
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/* Turn off all Tx DMA fifos */
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spin_lock(&trans_pcie->irq_lock);
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- iwl_pcie_txq_set_sched(trans, 0);
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+ iwl_scd_deactivate_fifos(trans);
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/* Stop each Tx DMA channel, and wait for it to be idle */
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for (ch = 0; ch < FH_TCSR_CHNL_NUM; ch++) {
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@@ -886,7 +876,7 @@ int iwl_pcie_tx_init(struct iwl_trans *trans)
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spin_lock(&trans_pcie->irq_lock);
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/* Turn off all Tx DMA fifos */
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- iwl_write_prph(trans, SCD_TXFACT, 0);
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+ iwl_scd_deactivate_fifos(trans);
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/* Tell NIC where to find the "keep warm" buffer */
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iwl_write_direct32(trans, FH_KW_MEM_ADDR_REG,
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@@ -1072,17 +1062,6 @@ static int iwl_pcie_txq_set_ratid_map(struct iwl_trans *trans, u16 ra_tid,
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return 0;
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}
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-static inline void iwl_pcie_txq_set_inactive(struct iwl_trans *trans,
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- u16 txq_id)
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-{
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- /* Simply stop the queue, but don't change any configuration;
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- * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
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- iwl_write_prph(trans,
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- SCD_QUEUE_STATUS_BITS(txq_id),
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- (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
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- (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
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-}
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-
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/* Receiver address (actually, Rx station's index into station table),
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* combined with Traffic ID (QOS priority), in format used by Tx Scheduler */
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#define BUILD_RAxTID(sta_id, tid) (((sta_id) << 4) + (tid))
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@@ -1096,11 +1075,11 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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WARN_ONCE(1, "queue %d already used - expect issues", txq_id);
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/* Stop this Tx queue before configuring it */
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- iwl_pcie_txq_set_inactive(trans, txq_id);
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+ iwl_scd_txq_set_inactive(trans, txq_id);
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/* Set this queue as a chain-building queue unless it is CMD queue */
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if (txq_id != trans_pcie->cmd_queue)
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- iwl_set_bits_prph(trans, SCD_QUEUECHAIN_SEL, BIT(txq_id));
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+ iwl_scd_txq_set_chain(trans, txq_id);
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/* If this queue is mapped to a certain station: it is an AGG queue */
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if (sta_id >= 0) {
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@@ -1110,7 +1089,7 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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iwl_pcie_txq_set_ratid_map(trans, ra_tid, txq_id);
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/* enable aggregations for the queue */
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- iwl_set_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
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+ iwl_scd_txq_enable_agg(trans, txq_id);
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trans_pcie->txq[txq_id].ampdu = true;
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} else {
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/*
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@@ -1118,7 +1097,7 @@ void iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int txq_id, int fifo,
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* ra_tid mapping configuration irrelevant since it is now a
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* non-AGG queue.
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*/
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- iwl_clear_bits_prph(trans, SCD_AGGR_SEL, BIT(txq_id));
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+ iwl_scd_txq_disable_agg(trans, txq_id);
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ssn = trans_pcie->txq[txq_id].q.read_ptr;
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}
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@@ -1172,7 +1151,7 @@ void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int txq_id)
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return;
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}
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- iwl_pcie_txq_set_inactive(trans, txq_id);
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+ iwl_scd_txq_set_inactive(trans, txq_id);
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iwl_trans_write_mem(trans, stts_addr, (void *)zero_val,
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ARRAY_SIZE(zero_val));
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