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@@ -60,6 +60,8 @@
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#include <linux/io.h>
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#include <linux/acpi.h>
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+#include "amba-pl011.h"
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+
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#define UART_NR 14
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#define SERIAL_AMBA_MAJOR 204
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@@ -71,11 +73,27 @@
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#define UART_DR_ERROR (UART011_DR_OE|UART011_DR_BE|UART011_DR_PE|UART011_DR_FE)
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#define UART_DUMMY_DR_RX (1 << 16)
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+static u16 pl011_std_offsets[REG_ARRAY_SIZE] = {
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+ [REG_DR] = UART01x_DR,
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+ [REG_FR] = UART01x_FR,
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+ [REG_LCRH_RX] = UART011_LCRH,
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+ [REG_LCRH_TX] = UART011_LCRH,
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+ [REG_IBRD] = UART011_IBRD,
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+ [REG_FBRD] = UART011_FBRD,
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+ [REG_CR] = UART011_CR,
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+ [REG_IFLS] = UART011_IFLS,
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+ [REG_IMSC] = UART011_IMSC,
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+ [REG_RIS] = UART011_RIS,
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+ [REG_MIS] = UART011_MIS,
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+ [REG_ICR] = UART011_ICR,
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+ [REG_DMACR] = UART011_DMACR,
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+};
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+
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/* There is by now at least one vendor with differing details, so handle it */
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struct vendor_data {
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+ const u16 *reg_offset;
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unsigned int ifls;
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- unsigned int lcrh_tx;
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- unsigned int lcrh_rx;
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+ bool access_32b;
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bool oversampling;
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bool dma_threshold;
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bool cts_event_workaround;
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@@ -91,9 +109,8 @@ static unsigned int get_fifosize_arm(struct amba_device *dev)
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}
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static struct vendor_data vendor_arm = {
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+ .reg_offset = pl011_std_offsets,
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.ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
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- .lcrh_tx = UART011_LCRH,
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- .lcrh_rx = UART011_LCRH,
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.oversampling = false,
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.dma_threshold = false,
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.cts_event_workaround = false,
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@@ -103,6 +120,7 @@ static struct vendor_data vendor_arm = {
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};
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static struct vendor_data vendor_sbsa = {
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+ .reg_offset = pl011_std_offsets,
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.oversampling = false,
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.dma_threshold = false,
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.cts_event_workaround = false,
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@@ -110,15 +128,41 @@ static struct vendor_data vendor_sbsa = {
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.fixed_options = true,
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};
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+static u16 pl011_st_offsets[REG_ARRAY_SIZE] = {
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+ [REG_DR] = UART01x_DR,
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+ [REG_ST_DMAWM] = ST_UART011_DMAWM,
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+ [REG_ST_TIMEOUT] = ST_UART011_TIMEOUT,
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+ [REG_FR] = UART01x_FR,
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+ [REG_LCRH_RX] = ST_UART011_LCRH_RX,
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+ [REG_LCRH_TX] = ST_UART011_LCRH_TX,
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+ [REG_IBRD] = UART011_IBRD,
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+ [REG_FBRD] = UART011_FBRD,
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+ [REG_CR] = UART011_CR,
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+ [REG_IFLS] = UART011_IFLS,
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+ [REG_IMSC] = UART011_IMSC,
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+ [REG_RIS] = UART011_RIS,
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+ [REG_MIS] = UART011_MIS,
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+ [REG_ICR] = UART011_ICR,
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+ [REG_DMACR] = UART011_DMACR,
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+ [REG_ST_XFCR] = ST_UART011_XFCR,
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+ [REG_ST_XON1] = ST_UART011_XON1,
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+ [REG_ST_XON2] = ST_UART011_XON2,
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+ [REG_ST_XOFF1] = ST_UART011_XOFF1,
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+ [REG_ST_XOFF2] = ST_UART011_XOFF2,
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+ [REG_ST_ITCR] = ST_UART011_ITCR,
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+ [REG_ST_ITIP] = ST_UART011_ITIP,
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+ [REG_ST_ABCR] = ST_UART011_ABCR,
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+ [REG_ST_ABIMSC] = ST_UART011_ABIMSC,
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+};
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+
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static unsigned int get_fifosize_st(struct amba_device *dev)
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{
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return 64;
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}
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static struct vendor_data vendor_st = {
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+ .reg_offset = pl011_st_offsets,
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.ifls = UART011_IFLS_RX_HALF|UART011_IFLS_TX_HALF,
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- .lcrh_tx = ST_UART011_LCRH_TX,
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- .lcrh_rx = ST_UART011_LCRH_RX,
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.oversampling = true,
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.dma_threshold = true,
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.cts_event_workaround = true,
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@@ -127,6 +171,29 @@ static struct vendor_data vendor_st = {
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.get_fifosize = get_fifosize_st,
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};
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+static const u16 pl011_zte_offsets[REG_ARRAY_SIZE] = {
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+ [REG_DR] = ZX_UART011_DR,
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+ [REG_FR] = ZX_UART011_FR,
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+ [REG_LCRH_RX] = ZX_UART011_LCRH,
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+ [REG_LCRH_TX] = ZX_UART011_LCRH,
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+ [REG_IBRD] = ZX_UART011_IBRD,
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+ [REG_FBRD] = ZX_UART011_FBRD,
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+ [REG_CR] = ZX_UART011_CR,
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+ [REG_IFLS] = ZX_UART011_IFLS,
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+ [REG_IMSC] = ZX_UART011_IMSC,
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+ [REG_RIS] = ZX_UART011_RIS,
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+ [REG_MIS] = ZX_UART011_MIS,
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+ [REG_ICR] = ZX_UART011_ICR,
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+ [REG_DMACR] = ZX_UART011_DMACR,
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+};
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+
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+static struct vendor_data vendor_zte = {
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+ .reg_offset = pl011_zte_offsets,
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+ .access_32b = true,
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+ .ifls = UART011_IFLS_RX4_8|UART011_IFLS_TX4_8,
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+ .get_fifosize = get_fifosize_arm,
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+};
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+
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/* Deals with DMA transactions */
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struct pl011_sgbuf {
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@@ -162,14 +229,13 @@ struct pl011_dmatx_data {
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*/
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struct uart_amba_port {
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struct uart_port port;
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+ const u16 *reg_offset;
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struct clk *clk;
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const struct vendor_data *vendor;
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unsigned int dmacr; /* dma control reg */
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unsigned int im; /* interrupt mask */
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unsigned int old_status;
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unsigned int fifosize; /* vendor-specific */
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- unsigned int lcrh_tx; /* vendor-specific */
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- unsigned int lcrh_rx; /* vendor-specific */
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unsigned int old_cr; /* state during shutdown */
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bool autorts;
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unsigned int fixed_baud; /* vendor-set fixed baud rate */
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@@ -184,6 +250,32 @@ struct uart_amba_port {
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#endif
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};
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+static unsigned int pl011_reg_to_offset(const struct uart_amba_port *uap,
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+ unsigned int reg)
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+{
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+ return uap->reg_offset[reg];
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+}
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+
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+static unsigned int pl011_read(const struct uart_amba_port *uap,
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+ unsigned int reg)
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+{
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+ void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
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+
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+ return (uap->port.iotype == UPIO_MEM32) ?
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+ readl_relaxed(addr) : readw_relaxed(addr);
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+}
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+
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+static void pl011_write(unsigned int val, const struct uart_amba_port *uap,
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+ unsigned int reg)
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+{
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+ void __iomem *addr = uap->port.membase + pl011_reg_to_offset(uap, reg);
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+
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+ if (uap->port.iotype == UPIO_MEM32)
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+ writel_relaxed(val, addr);
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+ else
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+ writew_relaxed(val, addr);
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+}
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+
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/*
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* Reads up to 256 characters from the FIFO or until it's empty and
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* inserts them into the TTY layer. Returns the number of characters
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@@ -196,13 +288,12 @@ static int pl011_fifo_to_tty(struct uart_amba_port *uap)
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int fifotaken = 0;
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while (max_count--) {
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- status = readw(uap->port.membase + UART01x_FR);
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+ status = pl011_read(uap, REG_FR);
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if (status & UART01x_FR_RXFE)
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break;
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/* Take chars from the FIFO and update status */
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- ch = readw(uap->port.membase + UART01x_DR) |
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- UART_DUMMY_DR_RX;
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+ ch = pl011_read(uap, REG_DR) | UART_DUMMY_DR_RX;
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flag = TTY_NORMAL;
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uap->port.icount.rx++;
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fifotaken++;
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@@ -284,7 +375,8 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
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struct amba_pl011_data *plat = dev_get_platdata(uap->port.dev);
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struct device *dev = uap->port.dev;
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struct dma_slave_config tx_conf = {
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- .dst_addr = uap->port.mapbase + UART01x_DR,
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+ .dst_addr = uap->port.mapbase +
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+ pl011_reg_to_offset(uap, REG_DR),
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.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
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.direction = DMA_MEM_TO_DEV,
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.dst_maxburst = uap->fifosize >> 1,
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@@ -339,7 +431,8 @@ static void pl011_dma_probe(struct uart_amba_port *uap)
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if (chan) {
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struct dma_slave_config rx_conf = {
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- .src_addr = uap->port.mapbase + UART01x_DR,
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+ .src_addr = uap->port.mapbase +
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+ pl011_reg_to_offset(uap, REG_DR),
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.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE,
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.direction = DMA_DEV_TO_MEM,
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.src_maxburst = uap->fifosize >> 2,
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@@ -438,7 +531,7 @@ static void pl011_dma_tx_callback(void *data)
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dmacr = uap->dmacr;
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uap->dmacr = dmacr & ~UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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/*
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* If TX DMA was disabled, it means that we've stopped the DMA for
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@@ -552,7 +645,7 @@ static int pl011_dma_tx_refill(struct uart_amba_port *uap)
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dma_dev->device_issue_pending(chan);
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uap->dmacr |= UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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uap->dmatx.queued = true;
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/*
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@@ -588,9 +681,9 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
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*/
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if (uap->dmatx.queued) {
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uap->dmacr |= UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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uap->im &= ~UART011_TXIM;
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- writew(uap->im, uap->port.membase + UART011_IMSC);
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+ pl011_write(uap->im, uap, REG_IMSC);
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return true;
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}
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@@ -600,7 +693,7 @@ static bool pl011_dma_tx_irq(struct uart_amba_port *uap)
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*/
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if (pl011_dma_tx_refill(uap) > 0) {
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uap->im &= ~UART011_TXIM;
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- writew(uap->im, uap->port.membase + UART011_IMSC);
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+ pl011_write(uap->im, uap, REG_IMSC);
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return true;
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}
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return false;
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@@ -614,7 +707,7 @@ static inline void pl011_dma_tx_stop(struct uart_amba_port *uap)
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{
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if (uap->dmatx.queued) {
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uap->dmacr &= ~UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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}
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}
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@@ -640,14 +733,12 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
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if (!uap->dmatx.queued) {
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if (pl011_dma_tx_refill(uap) > 0) {
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uap->im &= ~UART011_TXIM;
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- writew(uap->im, uap->port.membase +
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- UART011_IMSC);
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+ pl011_write(uap->im, uap, REG_IMSC);
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} else
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ret = false;
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} else if (!(uap->dmacr & UART011_TXDMAE)) {
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uap->dmacr |= UART011_TXDMAE;
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- writew(uap->dmacr,
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- uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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}
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return ret;
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}
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@@ -658,9 +749,9 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
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*/
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dmacr = uap->dmacr;
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uap->dmacr &= ~UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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- if (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF) {
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+ if (pl011_read(uap, REG_FR) & UART01x_FR_TXFF) {
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/*
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* No space in the FIFO, so enable the transmit interrupt
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* so we know when there is space. Note that once we've
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@@ -669,13 +760,13 @@ static inline bool pl011_dma_tx_start(struct uart_amba_port *uap)
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return false;
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}
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- writew(uap->port.x_char, uap->port.membase + UART01x_DR);
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+ pl011_write(uap->port.x_char, uap, REG_DR);
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uap->port.icount.tx++;
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uap->port.x_char = 0;
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/* Success - restore the DMA state */
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uap->dmacr = dmacr;
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- writew(dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(dmacr, uap, REG_DMACR);
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return true;
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}
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@@ -703,7 +794,7 @@ __acquires(&uap->port.lock)
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DMA_TO_DEVICE);
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uap->dmatx.queued = false;
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uap->dmacr &= ~UART011_TXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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}
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}
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@@ -743,11 +834,11 @@ static int pl011_dma_rx_trigger_dma(struct uart_amba_port *uap)
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dma_async_issue_pending(rxchan);
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uap->dmacr |= UART011_RXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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uap->dmarx.running = true;
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uap->im &= ~UART011_RXIM;
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- writew(uap->im, uap->port.membase + UART011_IMSC);
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+ pl011_write(uap->im, uap, REG_IMSC);
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return 0;
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}
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@@ -805,8 +896,8 @@ static void pl011_dma_rx_chars(struct uart_amba_port *uap,
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*/
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if (dma_count == pending && readfifo) {
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/* Clear any error flags */
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- writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS,
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- uap->port.membase + UART011_ICR);
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+ pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
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+ UART011_FEIS, uap, REG_ICR);
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/*
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* If we read all the DMA'd characters, and we had an
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@@ -854,7 +945,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
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/* Disable RX DMA - incoming data will wait in the FIFO */
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uap->dmacr &= ~UART011_RXDMAE;
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- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
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+ pl011_write(uap->dmacr, uap, REG_DMACR);
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uap->dmarx.running = false;
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pending = sgbuf->sg.length - state.residue;
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@@ -874,7 +965,7 @@ static void pl011_dma_rx_irq(struct uart_amba_port *uap)
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|
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
|
|
|
"fall back to interrupt mode\n");
|
|
|
uap->im |= UART011_RXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -922,7 +1013,7 @@ static void pl011_dma_rx_callback(void *data)
|
|
|
dev_dbg(uap->port.dev, "could not retrigger RX DMA job "
|
|
|
"fall back to interrupt mode\n");
|
|
|
uap->im |= UART011_RXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
}
|
|
|
}
|
|
|
|
|
@@ -935,7 +1026,7 @@ static inline void pl011_dma_rx_stop(struct uart_amba_port *uap)
|
|
|
{
|
|
|
/* FIXME. Just disable the DMA enable */
|
|
|
uap->dmacr &= ~UART011_RXDMAE;
|
|
|
- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
|
+ pl011_write(uap->dmacr, uap, REG_DMACR);
|
|
|
}
|
|
|
|
|
|
/*
|
|
@@ -979,7 +1070,7 @@ static void pl011_dma_rx_poll(unsigned long args)
|
|
|
spin_lock_irqsave(&uap->port.lock, flags);
|
|
|
pl011_dma_rx_stop(uap);
|
|
|
uap->im |= UART011_RXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
spin_unlock_irqrestore(&uap->port.lock, flags);
|
|
|
|
|
|
uap->dmarx.running = false;
|
|
@@ -1041,7 +1132,7 @@ static void pl011_dma_startup(struct uart_amba_port *uap)
|
|
|
skip_rx:
|
|
|
/* Turn on DMA error (RX/TX will be enabled on demand) */
|
|
|
uap->dmacr |= UART011_DMAONERR;
|
|
|
- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
|
+ pl011_write(uap->dmacr, uap, REG_DMACR);
|
|
|
|
|
|
/*
|
|
|
* ST Micro variants has some specific dma burst threshold
|
|
@@ -1049,8 +1140,8 @@ skip_rx:
|
|
|
* be issued above/below 16 bytes.
|
|
|
*/
|
|
|
if (uap->vendor->dma_threshold)
|
|
|
- writew(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
|
|
|
- uap->port.membase + ST_UART011_DMAWM);
|
|
|
+ pl011_write(ST_UART011_DMAWM_RX_16 | ST_UART011_DMAWM_TX_16,
|
|
|
+ uap, REG_ST_DMAWM);
|
|
|
|
|
|
if (uap->using_rx_dma) {
|
|
|
if (pl011_dma_rx_trigger_dma(uap))
|
|
@@ -1075,12 +1166,12 @@ static void pl011_dma_shutdown(struct uart_amba_port *uap)
|
|
|
return;
|
|
|
|
|
|
/* Disable RX and TX DMA */
|
|
|
- while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_BUSY)
|
|
|
+ while (pl011_read(uap, REG_FR) & UART01x_FR_BUSY)
|
|
|
barrier();
|
|
|
|
|
|
spin_lock_irq(&uap->port.lock);
|
|
|
uap->dmacr &= ~(UART011_DMAONERR | UART011_RXDMAE | UART011_TXDMAE);
|
|
|
- writew(uap->dmacr, uap->port.membase + UART011_DMACR);
|
|
|
+ pl011_write(uap->dmacr, uap, REG_DMACR);
|
|
|
spin_unlock_irq(&uap->port.lock);
|
|
|
|
|
|
if (uap->using_tx_dma) {
|
|
@@ -1181,7 +1272,7 @@ static void pl011_stop_tx(struct uart_port *port)
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
|
|
|
uap->im &= ~UART011_TXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
pl011_dma_tx_stop(uap);
|
|
|
}
|
|
|
|
|
@@ -1191,7 +1282,7 @@ static void pl011_tx_chars(struct uart_amba_port *uap, bool from_irq);
|
|
|
static void pl011_start_tx_pio(struct uart_amba_port *uap)
|
|
|
{
|
|
|
uap->im |= UART011_TXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
pl011_tx_chars(uap, false);
|
|
|
}
|
|
|
|
|
@@ -1211,7 +1302,7 @@ static void pl011_stop_rx(struct uart_port *port)
|
|
|
|
|
|
uap->im &= ~(UART011_RXIM|UART011_RTIM|UART011_FEIM|
|
|
|
UART011_PEIM|UART011_BEIM|UART011_OEIM);
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
|
|
|
pl011_dma_rx_stop(uap);
|
|
|
}
|
|
@@ -1222,7 +1313,7 @@ static void pl011_enable_ms(struct uart_port *port)
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
|
|
|
uap->im |= UART011_RIMIM|UART011_CTSMIM|UART011_DCDMIM|UART011_DSRMIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
}
|
|
|
|
|
|
static void pl011_rx_chars(struct uart_amba_port *uap)
|
|
@@ -1242,7 +1333,7 @@ __acquires(&uap->port.lock)
|
|
|
dev_dbg(uap->port.dev, "could not trigger RX DMA job "
|
|
|
"fall back to interrupt mode again\n");
|
|
|
uap->im |= UART011_RXIM;
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
} else {
|
|
|
#ifdef CONFIG_DMA_ENGINE
|
|
|
/* Start Rx DMA poll */
|
|
@@ -1263,10 +1354,10 @@ static bool pl011_tx_char(struct uart_amba_port *uap, unsigned char c,
|
|
|
bool from_irq)
|
|
|
{
|
|
|
if (unlikely(!from_irq) &&
|
|
|
- readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
|
|
|
+ pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
|
|
|
return false; /* unable to transmit character */
|
|
|
|
|
|
- writew(c, uap->port.membase + UART01x_DR);
|
|
|
+ pl011_write(c, uap, REG_DR);
|
|
|
uap->port.icount.tx++;
|
|
|
|
|
|
return true;
|
|
@@ -1313,7 +1404,7 @@ static void pl011_modem_status(struct uart_amba_port *uap)
|
|
|
{
|
|
|
unsigned int status, delta;
|
|
|
|
|
|
- status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
|
|
|
+ status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
|
|
|
|
|
|
delta = status ^ uap->old_status;
|
|
|
uap->old_status = status;
|
|
@@ -1341,15 +1432,15 @@ static void check_apply_cts_event_workaround(struct uart_amba_port *uap)
|
|
|
return;
|
|
|
|
|
|
/* workaround to make sure that all bits are unlocked.. */
|
|
|
- writew(0x00, uap->port.membase + UART011_ICR);
|
|
|
+ pl011_write(0x00, uap, REG_ICR);
|
|
|
|
|
|
/*
|
|
|
* WA: introduce 26ns(1 uart clk) delay before W1C;
|
|
|
* single apb access will incur 2 pclk(133.12Mhz) delay,
|
|
|
* so add 2 dummy reads
|
|
|
*/
|
|
|
- dummy_read = readw(uap->port.membase + UART011_ICR);
|
|
|
- dummy_read = readw(uap->port.membase + UART011_ICR);
|
|
|
+ dummy_read = pl011_read(uap, REG_ICR);
|
|
|
+ dummy_read = pl011_read(uap, REG_ICR);
|
|
|
}
|
|
|
|
|
|
static irqreturn_t pl011_int(int irq, void *dev_id)
|
|
@@ -1361,15 +1452,15 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
|
|
|
int handled = 0;
|
|
|
|
|
|
spin_lock_irqsave(&uap->port.lock, flags);
|
|
|
- imsc = readw(uap->port.membase + UART011_IMSC);
|
|
|
- status = readw(uap->port.membase + UART011_RIS) & imsc;
|
|
|
+ imsc = pl011_read(uap, REG_IMSC);
|
|
|
+ status = pl011_read(uap, REG_RIS) & imsc;
|
|
|
if (status) {
|
|
|
do {
|
|
|
check_apply_cts_event_workaround(uap);
|
|
|
|
|
|
- writew(status & ~(UART011_TXIS|UART011_RTIS|
|
|
|
- UART011_RXIS),
|
|
|
- uap->port.membase + UART011_ICR);
|
|
|
+ pl011_write(status & ~(UART011_TXIS|UART011_RTIS|
|
|
|
+ UART011_RXIS),
|
|
|
+ uap, REG_ICR);
|
|
|
|
|
|
if (status & (UART011_RTIS|UART011_RXIS)) {
|
|
|
if (pl011_dma_rx_running(uap))
|
|
@@ -1386,7 +1477,7 @@ static irqreturn_t pl011_int(int irq, void *dev_id)
|
|
|
if (pass_counter-- == 0)
|
|
|
break;
|
|
|
|
|
|
- status = readw(uap->port.membase + UART011_RIS) & imsc;
|
|
|
+ status = pl011_read(uap, REG_RIS) & imsc;
|
|
|
} while (status != 0);
|
|
|
handled = 1;
|
|
|
}
|
|
@@ -1400,7 +1491,7 @@ static unsigned int pl011_tx_empty(struct uart_port *port)
|
|
|
{
|
|
|
struct uart_amba_port *uap =
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
- unsigned int status = readw(uap->port.membase + UART01x_FR);
|
|
|
+ unsigned int status = pl011_read(uap, REG_FR);
|
|
|
return status & (UART01x_FR_BUSY|UART01x_FR_TXFF) ? 0 : TIOCSER_TEMT;
|
|
|
}
|
|
|
|
|
@@ -1409,7 +1500,7 @@ static unsigned int pl011_get_mctrl(struct uart_port *port)
|
|
|
struct uart_amba_port *uap =
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
unsigned int result = 0;
|
|
|
- unsigned int status = readw(uap->port.membase + UART01x_FR);
|
|
|
+ unsigned int status = pl011_read(uap, REG_FR);
|
|
|
|
|
|
#define TIOCMBIT(uartbit, tiocmbit) \
|
|
|
if (status & uartbit) \
|
|
@@ -1429,7 +1520,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
unsigned int cr;
|
|
|
|
|
|
- cr = readw(uap->port.membase + UART011_CR);
|
|
|
+ cr = pl011_read(uap, REG_CR);
|
|
|
|
|
|
#define TIOCMBIT(tiocmbit, uartbit) \
|
|
|
if (mctrl & tiocmbit) \
|
|
@@ -1449,7 +1540,7 @@ static void pl011_set_mctrl(struct uart_port *port, unsigned int mctrl)
|
|
|
}
|
|
|
#undef TIOCMBIT
|
|
|
|
|
|
- writew(cr, uap->port.membase + UART011_CR);
|
|
|
+ pl011_write(cr, uap, REG_CR);
|
|
|
}
|
|
|
|
|
|
static void pl011_break_ctl(struct uart_port *port, int break_state)
|
|
@@ -1460,12 +1551,12 @@ static void pl011_break_ctl(struct uart_port *port, int break_state)
|
|
|
unsigned int lcr_h;
|
|
|
|
|
|
spin_lock_irqsave(&uap->port.lock, flags);
|
|
|
- lcr_h = readw(uap->port.membase + uap->lcrh_tx);
|
|
|
+ lcr_h = pl011_read(uap, REG_LCRH_TX);
|
|
|
if (break_state == -1)
|
|
|
lcr_h |= UART01x_LCRH_BRK;
|
|
|
else
|
|
|
lcr_h &= ~UART01x_LCRH_BRK;
|
|
|
- writew(lcr_h, uap->port.membase + uap->lcrh_tx);
|
|
|
+ pl011_write(lcr_h, uap, REG_LCRH_TX);
|
|
|
spin_unlock_irqrestore(&uap->port.lock, flags);
|
|
|
}
|
|
|
|
|
@@ -1475,9 +1566,8 @@ static void pl011_quiesce_irqs(struct uart_port *port)
|
|
|
{
|
|
|
struct uart_amba_port *uap =
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
- unsigned char __iomem *regs = uap->port.membase;
|
|
|
|
|
|
- writew(readw(regs + UART011_MIS), regs + UART011_ICR);
|
|
|
+ pl011_write(pl011_read(uap, REG_MIS), uap, REG_ICR);
|
|
|
/*
|
|
|
* There is no way to clear TXIM as this is "ready to transmit IRQ", so
|
|
|
* we simply mask it. start_tx() will unmask it.
|
|
@@ -1491,7 +1581,8 @@ static void pl011_quiesce_irqs(struct uart_port *port)
|
|
|
* (including tx queue), so we're also fine with start_tx()'s caller
|
|
|
* side.
|
|
|
*/
|
|
|
- writew(readw(regs + UART011_IMSC) & ~UART011_TXIM, regs + UART011_IMSC);
|
|
|
+ pl011_write(pl011_read(uap, REG_IMSC) & ~UART011_TXIM, uap,
|
|
|
+ REG_IMSC);
|
|
|
}
|
|
|
|
|
|
static int pl011_get_poll_char(struct uart_port *port)
|
|
@@ -1506,11 +1597,11 @@ static int pl011_get_poll_char(struct uart_port *port)
|
|
|
*/
|
|
|
pl011_quiesce_irqs(port);
|
|
|
|
|
|
- status = readw(uap->port.membase + UART01x_FR);
|
|
|
+ status = pl011_read(uap, REG_FR);
|
|
|
if (status & UART01x_FR_RXFE)
|
|
|
return NO_POLL_CHAR;
|
|
|
|
|
|
- return readw(uap->port.membase + UART01x_DR);
|
|
|
+ return pl011_read(uap, REG_DR);
|
|
|
}
|
|
|
|
|
|
static void pl011_put_poll_char(struct uart_port *port,
|
|
@@ -1519,10 +1610,10 @@ static void pl011_put_poll_char(struct uart_port *port,
|
|
|
struct uart_amba_port *uap =
|
|
|
container_of(port, struct uart_amba_port, port);
|
|
|
|
|
|
- while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
|
|
|
+ while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
|
|
|
barrier();
|
|
|
|
|
|
- writew(ch, uap->port.membase + UART01x_DR);
|
|
|
+ pl011_write(ch, uap, REG_DR);
|
|
|
}
|
|
|
|
|
|
#endif /* CONFIG_CONSOLE_POLL */
|
|
@@ -1546,15 +1637,16 @@ static int pl011_hwinit(struct uart_port *port)
|
|
|
uap->port.uartclk = clk_get_rate(uap->clk);
|
|
|
|
|
|
/* Clear pending error and receive interrupts */
|
|
|
- writew(UART011_OEIS | UART011_BEIS | UART011_PEIS | UART011_FEIS |
|
|
|
- UART011_RTIS | UART011_RXIS, uap->port.membase + UART011_ICR);
|
|
|
+ pl011_write(UART011_OEIS | UART011_BEIS | UART011_PEIS |
|
|
|
+ UART011_FEIS | UART011_RTIS | UART011_RXIS,
|
|
|
+ uap, REG_ICR);
|
|
|
|
|
|
/*
|
|
|
* Save interrupts enable mask, and enable RX interrupts in case if
|
|
|
* the interrupt is used for NMI entry.
|
|
|
*/
|
|
|
- uap->im = readw(uap->port.membase + UART011_IMSC);
|
|
|
- writew(UART011_RTIM | UART011_RXIM, uap->port.membase + UART011_IMSC);
|
|
|
+ uap->im = pl011_read(uap, REG_IMSC);
|
|
|
+ pl011_write(UART011_RTIM | UART011_RXIM, uap, REG_IMSC);
|
|
|
|
|
|
if (dev_get_platdata(uap->port.dev)) {
|
|
|
struct amba_pl011_data *plat;
|
|
@@ -1566,24 +1658,30 @@ static int pl011_hwinit(struct uart_port *port)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+static bool pl011_split_lcrh(const struct uart_amba_port *uap)
|
|
|
+{
|
|
|
+ return pl011_reg_to_offset(uap, REG_LCRH_RX) !=
|
|
|
+ pl011_reg_to_offset(uap, REG_LCRH_TX);
|
|
|
+}
|
|
|
+
|
|
|
static void pl011_write_lcr_h(struct uart_amba_port *uap, unsigned int lcr_h)
|
|
|
{
|
|
|
- writew(lcr_h, uap->port.membase + uap->lcrh_rx);
|
|
|
- if (uap->lcrh_rx != uap->lcrh_tx) {
|
|
|
+ pl011_write(lcr_h, uap, REG_LCRH_RX);
|
|
|
+ if (pl011_split_lcrh(uap)) {
|
|
|
int i;
|
|
|
/*
|
|
|
* Wait 10 PCLKs before writing LCRH_TX register,
|
|
|
* to get this delay write read only register 10 times
|
|
|
*/
|
|
|
for (i = 0; i < 10; ++i)
|
|
|
- writew(0xff, uap->port.membase + UART011_MIS);
|
|
|
- writew(lcr_h, uap->port.membase + uap->lcrh_tx);
|
|
|
+ pl011_write(0xff, uap, REG_MIS);
|
|
|
+ pl011_write(lcr_h, uap, REG_LCRH_TX);
|
|
|
}
|
|
|
}
|
|
|
|
|
|
static int pl011_allocate_irq(struct uart_amba_port *uap)
|
|
|
{
|
|
|
- writew(uap->im, uap->port.membase + UART011_IMSC);
|
|
|
+ pl011_write(uap->im, uap, REG_IMSC);
|
|
|
|
|
|
return request_irq(uap->port.irq, pl011_int, 0, "uart-pl011", uap);
|
|
|
}
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@@ -1598,12 +1696,11 @@ static void pl011_enable_interrupts(struct uart_amba_port *uap)
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spin_lock_irq(&uap->port.lock);
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/* Clear out any spuriously appearing RX interrupts */
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- writew(UART011_RTIS | UART011_RXIS,
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- uap->port.membase + UART011_ICR);
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+ pl011_write(UART011_RTIS | UART011_RXIS, uap, REG_ICR);
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uap->im = UART011_RTIM;
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if (!pl011_dma_rx_running(uap))
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uap->im |= UART011_RXIM;
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- writew(uap->im, uap->port.membase + UART011_IMSC);
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+ pl011_write(uap->im, uap, REG_IMSC);
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spin_unlock_irq(&uap->port.lock);
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}
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@@ -1622,21 +1719,21 @@ static int pl011_startup(struct uart_port *port)
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if (retval)
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goto clk_dis;
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- writew(uap->vendor->ifls, uap->port.membase + UART011_IFLS);
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+ pl011_write(uap->vendor->ifls, uap, REG_IFLS);
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spin_lock_irq(&uap->port.lock);
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/* restore RTS and DTR */
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cr = uap->old_cr & (UART011_CR_RTS | UART011_CR_DTR);
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cr |= UART01x_CR_UARTEN | UART011_CR_RXE | UART011_CR_TXE;
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- writew(cr, uap->port.membase + UART011_CR);
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+ pl011_write(cr, uap, REG_CR);
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spin_unlock_irq(&uap->port.lock);
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/*
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* initialise the old status of the modem signals
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*/
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- uap->old_status = readw(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
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+ uap->old_status = pl011_read(uap, REG_FR) & UART01x_FR_MODEM_ANY;
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/* Startup DMA */
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pl011_dma_startup(uap);
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@@ -1677,9 +1774,9 @@ static void pl011_shutdown_channel(struct uart_amba_port *uap,
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{
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unsigned long val;
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- val = readw(uap->port.membase + lcrh);
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+ val = pl011_read(uap, lcrh);
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val &= ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN);
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- writew(val, uap->port.membase + lcrh);
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+ pl011_write(val, uap, lcrh);
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}
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/*
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@@ -1693,19 +1790,19 @@ static void pl011_disable_uart(struct uart_amba_port *uap)
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uap->autorts = false;
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spin_lock_irq(&uap->port.lock);
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- cr = readw(uap->port.membase + UART011_CR);
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+ cr = pl011_read(uap, REG_CR);
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uap->old_cr = cr;
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cr &= UART011_CR_RTS | UART011_CR_DTR;
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cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
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- writew(cr, uap->port.membase + UART011_CR);
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+ pl011_write(cr, uap, REG_CR);
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spin_unlock_irq(&uap->port.lock);
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/*
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* disable break condition and fifos
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*/
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- pl011_shutdown_channel(uap, uap->lcrh_rx);
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- if (uap->lcrh_rx != uap->lcrh_tx)
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- pl011_shutdown_channel(uap, uap->lcrh_tx);
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+ pl011_shutdown_channel(uap, REG_LCRH_RX);
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+ if (pl011_split_lcrh(uap))
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+ pl011_shutdown_channel(uap, REG_LCRH_TX);
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}
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static void pl011_disable_interrupts(struct uart_amba_port *uap)
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@@ -1714,8 +1811,8 @@ static void pl011_disable_interrupts(struct uart_amba_port *uap)
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/* mask all interrupts and clear all pending ones */
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uap->im = 0;
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- writew(uap->im, uap->port.membase + UART011_IMSC);
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- writew(0xffff, uap->port.membase + UART011_ICR);
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+ pl011_write(uap->im, uap, REG_IMSC);
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+ pl011_write(0xffff, uap, REG_ICR);
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spin_unlock_irq(&uap->port.lock);
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}
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@@ -1867,8 +1964,8 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
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pl011_enable_ms(port);
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/* first, disable everything */
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- old_cr = readw(port->membase + UART011_CR);
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- writew(0, port->membase + UART011_CR);
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+ old_cr = pl011_read(uap, REG_CR);
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+ pl011_write(0, uap, REG_CR);
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if (termios->c_cflag & CRTSCTS) {
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if (old_cr & UART011_CR_RTS)
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@@ -1901,17 +1998,17 @@ pl011_set_termios(struct uart_port *port, struct ktermios *termios,
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quot -= 2;
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}
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/* Set baud rate */
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- writew(quot & 0x3f, port->membase + UART011_FBRD);
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- writew(quot >> 6, port->membase + UART011_IBRD);
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+ pl011_write(quot & 0x3f, uap, REG_FBRD);
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+ pl011_write(quot >> 6, uap, REG_IBRD);
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/*
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* ----------v----------v----------v----------v-----
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- * NOTE: lcrh_tx and lcrh_rx MUST BE WRITTEN AFTER
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- * UART011_FBRD & UART011_IBRD.
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+ * NOTE: REG_LCRH_TX and REG_LCRH_RX MUST BE WRITTEN AFTER
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+ * REG_FBRD & REG_IBRD.
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* ----------^----------^----------^----------^-----
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*/
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pl011_write_lcr_h(uap, lcr_h);
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- writew(old_cr, port->membase + UART011_CR);
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+ pl011_write(old_cr, uap, REG_CR);
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spin_unlock_irqrestore(&port->lock, flags);
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}
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@@ -2052,9 +2149,9 @@ static void pl011_console_putchar(struct uart_port *port, int ch)
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struct uart_amba_port *uap =
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container_of(port, struct uart_amba_port, port);
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- while (readw(uap->port.membase + UART01x_FR) & UART01x_FR_TXFF)
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+ while (pl011_read(uap, REG_FR) & UART01x_FR_TXFF)
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barrier();
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- writew(ch, uap->port.membase + UART01x_DR);
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+ pl011_write(ch, uap, REG_DR);
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}
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static void
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@@ -2079,10 +2176,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
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* First save the CR then disable the interrupts
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*/
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if (!uap->vendor->always_enabled) {
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- old_cr = readw(uap->port.membase + UART011_CR);
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+ old_cr = pl011_read(uap, REG_CR);
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new_cr = old_cr & ~UART011_CR_CTSEN;
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new_cr |= UART01x_CR_UARTEN | UART011_CR_TXE;
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- writew(new_cr, uap->port.membase + UART011_CR);
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+ pl011_write(new_cr, uap, REG_CR);
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}
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uart_console_write(&uap->port, s, count, pl011_console_putchar);
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@@ -2092,10 +2189,10 @@ pl011_console_write(struct console *co, const char *s, unsigned int count)
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* and restore the TCR
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*/
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do {
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- status = readw(uap->port.membase + UART01x_FR);
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+ status = pl011_read(uap, REG_FR);
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} while (status & UART01x_FR_BUSY);
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if (!uap->vendor->always_enabled)
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- writew(old_cr, uap->port.membase + UART011_CR);
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+ pl011_write(old_cr, uap, REG_CR);
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if (locked)
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spin_unlock(&uap->port.lock);
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@@ -2108,10 +2205,10 @@ static void __init
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pl011_console_get_options(struct uart_amba_port *uap, int *baud,
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int *parity, int *bits)
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{
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- if (readw(uap->port.membase + UART011_CR) & UART01x_CR_UARTEN) {
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+ if (pl011_read(uap, REG_CR) & UART01x_CR_UARTEN) {
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unsigned int lcr_h, ibrd, fbrd;
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- lcr_h = readw(uap->port.membase + uap->lcrh_tx);
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+ lcr_h = pl011_read(uap, REG_LCRH_TX);
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*parity = 'n';
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if (lcr_h & UART01x_LCRH_PEN) {
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@@ -2126,13 +2223,13 @@ pl011_console_get_options(struct uart_amba_port *uap, int *baud,
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else
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*bits = 8;
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- ibrd = readw(uap->port.membase + UART011_IBRD);
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- fbrd = readw(uap->port.membase + UART011_FBRD);
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+ ibrd = pl011_read(uap, REG_IBRD);
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+ fbrd = pl011_read(uap, REG_FBRD);
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*baud = uap->port.uartclk * 4 / (64 * ibrd + fbrd);
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if (uap->vendor->oversampling) {
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- if (readw(uap->port.membase + UART011_CR)
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+ if (pl011_read(uap, REG_CR)
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& ST_UART011_CR_OVSFACT)
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*baud *= 2;
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}
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@@ -2206,7 +2303,10 @@ static void pl011_putc(struct uart_port *port, int c)
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{
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while (readl(port->membase + UART01x_FR) & UART01x_FR_TXFF)
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;
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- writeb(c, port->membase + UART01x_DR);
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+ if (port->iotype == UPIO_MEM32)
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+ writel(c, port->membase + UART01x_DR);
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+ else
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+ writeb(c, port->membase + UART01x_DR);
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while (readl(port->membase + UART01x_FR) & UART01x_FR_BUSY)
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;
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}
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@@ -2319,7 +2419,6 @@ static int pl011_setup_port(struct device *dev, struct uart_amba_port *uap,
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uap->port.dev = dev;
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uap->port.mapbase = mmiobase->start;
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uap->port.membase = base;
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- uap->port.iotype = UPIO_MEM;
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uap->port.fifosize = uap->fifosize;
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uap->port.flags = UPF_BOOT_AUTOCONF;
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uap->port.line = index;
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@@ -2334,8 +2433,8 @@ static int pl011_register_port(struct uart_amba_port *uap)
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int ret;
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/* Ensure interrupts from this UART are masked and cleared */
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- writew(0, uap->port.membase + UART011_IMSC);
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- writew(0xffff, uap->port.membase + UART011_ICR);
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+ pl011_write(0, uap, REG_IMSC);
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+ pl011_write(0xffff, uap, REG_ICR);
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if (!amba_reg.state) {
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ret = uart_register_driver(&amba_reg);
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@@ -2372,10 +2471,10 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id)
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if (IS_ERR(uap->clk))
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return PTR_ERR(uap->clk);
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+ uap->reg_offset = vendor->reg_offset;
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uap->vendor = vendor;
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- uap->lcrh_rx = vendor->lcrh_rx;
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- uap->lcrh_tx = vendor->lcrh_tx;
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uap->fifosize = vendor->get_fifosize(dev);
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+ uap->port.iotype = vendor->access_32b ? UPIO_MEM32 : UPIO_MEM;
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uap->port.irq = dev->irq[0];
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uap->port.ops = &amba_pl011_pops;
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@@ -2453,8 +2552,10 @@ static int sbsa_uart_probe(struct platform_device *pdev)
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if (!uap)
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return -ENOMEM;
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+ uap->reg_offset = vendor_sbsa.reg_offset;
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uap->vendor = &vendor_sbsa;
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uap->fifosize = 32;
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+ uap->port.iotype = vendor_sbsa.access_32b ? UPIO_MEM32 : UPIO_MEM;
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uap->port.irq = platform_get_irq(pdev, 0);
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uap->port.ops = &sbsa_uart_pops;
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uap->fixed_baud = baudrate;
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