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ARC: dma [IOC]: mark DMA devices connected as dma-coherent

Mark DMA devices on AXS103 and HSDK boards connected through IOC
port as dma-coherent.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
Eugeniy Paltsev 7 жил өмнө
parent
commit
678c8110d2

+ 26 - 0
arch/arc/boot/dts/axc003.dtsi

@@ -93,6 +93,32 @@
 		};
 		};
 	};
 	};
 
 
+	/*
+	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
+	 * it via overlay because peripherals defined in axs10x_mb.dtsi are
+	 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
+	 * only AXS103 board has HW-coherent DMA peripherals)
+	 * We don't need to mark pgu@17000 as dma-coherent because it uses
+	 * external DMA buffer located outside of IOC aperture.
+	 */
+	axs10x_mb {
+		ethernet@0x18000 {
+			dma-coherent;
+		};
+
+		ehci@0x40000 {
+			dma-coherent;
+		};
+
+		ohci@0x60000 {
+			dma-coherent;
+		};
+
+		mmc@0x15000 {
+			dma-coherent;
+		};
+	};
+
 	/*
 	/*
 	 * The DW APB ICTL intc on MB is connected to CPU intc via a
 	 * The DW APB ICTL intc on MB is connected to CPU intc via a
 	 * DT "invisible" DW APB GPIO block, configured to simply pass thru
 	 * DT "invisible" DW APB GPIO block, configured to simply pass thru

+ 26 - 0
arch/arc/boot/dts/axc003_idu.dtsi

@@ -100,6 +100,32 @@
 		};
 		};
 	};
 	};
 
 
+	/*
+	 * Mark DMA peripherals connected via IOC port as dma-coherent. We do
+	 * it via overlay because peripherals defined in axs10x_mb.dtsi are
+	 * used for both AXS101 and AXS103 boards and only AXS103 has IOC (so
+	 * only AXS103 board has HW-coherent DMA peripherals)
+	 * We don't need to mark pgu@17000 as dma-coherent because it uses
+	 * external DMA buffer located outside of IOC aperture.
+	 */
+	axs10x_mb {
+		ethernet@0x18000 {
+			dma-coherent;
+		};
+
+		ehci@0x40000 {
+			dma-coherent;
+		};
+
+		ohci@0x60000 {
+			dma-coherent;
+		};
+
+		mmc@0x15000 {
+			dma-coherent;
+		};
+	};
+
 	/*
 	/*
 	 * This INTC is actually connected to DW APB GPIO
 	 * This INTC is actually connected to DW APB GPIO
 	 * which acts as a wire between MB INTC and CPU INTC.
 	 * which acts as a wire between MB INTC and CPU INTC.

+ 4 - 0
arch/arc/boot/dts/hsdk.dts

@@ -181,6 +181,7 @@
 			resets = <&cgu_rst HSDK_ETH_RESET>;
 			resets = <&cgu_rst HSDK_ETH_RESET>;
 			reset-names = "stmmaceth";
 			reset-names = "stmmaceth";
 			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
 			mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
+			dma-coherent;
 
 
 			mdio {
 			mdio {
 				#address-cells = <1>;
 				#address-cells = <1>;
@@ -199,12 +200,14 @@
 			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
 			compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
 			reg = <0x60000 0x100>;
 			reg = <0x60000 0x100>;
 			interrupts = <15>;
 			interrupts = <15>;
+			dma-coherent;
 		};
 		};
 
 
 		ehci@40000 {
 		ehci@40000 {
 			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
 			compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
 			reg = <0x40000 0x100>;
 			reg = <0x40000 0x100>;
 			interrupts = <15>;
 			interrupts = <15>;
+			dma-coherent;
 		};
 		};
 
 
 		mmc@a000 {
 		mmc@a000 {
@@ -217,6 +220,7 @@
 			clock-names = "biu", "ciu";
 			clock-names = "biu", "ciu";
 			interrupts = <12>;
 			interrupts = <12>;
 			bus-width = <4>;
 			bus-width = <4>;
+			dma-coherent;
 		};
 		};
 	};
 	};