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@@ -24,8 +24,8 @@ enum s2mps11_irq {
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTC60S,
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+ S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA1,
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- S2MPS11_IRQ_RTCA2,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_WTSR,
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@@ -47,7 +47,7 @@ enum s2mps11_irq {
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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-#define S2MPS11_IRQ_RTCA2_MASK (1 << 2)
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+#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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