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@@ -748,7 +748,7 @@ static void amdgpu_vm_frag_ptes(struct amdgpu_device *adev,
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* @vm: requested vm
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* @start: start of GPU address range
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* @end: end of GPU address range
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- * @dst: destination address to map to
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+ * @dst: destination address to map to, the next dst inside the function
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* @flags: mapping flags
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*
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* Update the page tables in the range @start - @end.
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@@ -762,43 +762,43 @@ static void amdgpu_vm_update_ptes(struct amdgpu_device *adev,
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{
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const uint64_t mask = AMDGPU_VM_PTE_COUNT - 1;
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- uint64_t last_pe_start = ~0, last_pe_end = ~0, last_dst = ~0;
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- uint64_t addr;
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+ uint64_t cur_pe_start = ~0, cur_pe_end = ~0, cur_dst = ~0;
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+ uint64_t addr; /* next GPU address to be updated */
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/* walk over the address space and update the page tables */
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for (addr = start; addr < end; ) {
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uint64_t pt_idx = addr >> amdgpu_vm_block_size;
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struct amdgpu_bo *pt = vm->page_tables[pt_idx].entry.robj;
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- unsigned nptes;
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- uint64_t pe_start;
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+ unsigned nptes; /* next number of ptes to be updated */
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+ uint64_t next_pe_start;
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if ((addr & ~mask) == (end & ~mask))
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nptes = end - addr;
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else
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nptes = AMDGPU_VM_PTE_COUNT - (addr & mask);
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- pe_start = amdgpu_bo_gpu_offset(pt);
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- pe_start += (addr & mask) * 8;
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+ next_pe_start = amdgpu_bo_gpu_offset(pt);
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+ next_pe_start += (addr & mask) * 8;
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- if (last_pe_end != pe_start) {
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+ if (cur_pe_end != next_pe_start) {
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amdgpu_vm_frag_ptes(adev, vm_update_params,
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- last_pe_start, last_pe_end,
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- last_dst, flags);
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+ cur_pe_start, cur_pe_end,
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+ cur_dst, flags);
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- last_pe_start = pe_start;
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- last_pe_end = pe_start + 8 * nptes;
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- last_dst = dst;
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+ cur_pe_start = next_pe_start;
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+ cur_pe_end = next_pe_start + 8 * nptes;
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+ cur_dst = dst;
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} else {
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- last_pe_end += 8 * nptes;
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+ cur_pe_end += 8 * nptes;
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}
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addr += nptes;
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dst += nptes * AMDGPU_GPU_PAGE_SIZE;
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}
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- amdgpu_vm_frag_ptes(adev, vm_update_params, last_pe_start,
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- last_pe_end, last_dst, flags);
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+ amdgpu_vm_frag_ptes(adev, vm_update_params, cur_pe_start,
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+ cur_pe_end, cur_dst, flags);
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}
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/**
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