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@@ -46,10 +46,10 @@
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#define SACR0_STRF (1 << 5) /* FIFO Select for EFWR Special Function */
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#define SACR0_EFWR (1 << 4) /* Enable EFWR Function */
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#define SACR0_RST (1 << 3) /* FIFO, i2s Register Reset */
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-#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
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+#define SACR0_BCKD (1 << 2) /* Bit Clock Direction */
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#define SACR0_ENB (1 << 0) /* Enable I2S Link */
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#define SACR1_ENLBF (1 << 5) /* Enable Loopback */
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-#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
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+#define SACR1_DRPL (1 << 4) /* Disable Replaying Function */
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#define SACR1_DREC (1 << 3) /* Disable Recording Function */
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#define SACR1_AMSL (1 << 0) /* Specify Alternate Mode */
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@@ -60,7 +60,7 @@
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#define SASR0_TFS (1 << 3) /* Tx FIFO Service Request */
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#define SASR0_BSY (1 << 2) /* I2S Busy */
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#define SASR0_RNE (1 << 1) /* Rx FIFO Not Empty */
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-#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
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+#define SASR0_TNF (1 << 0) /* Tx FIFO Not Empty */
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#define SAICR_ROR (1 << 6) /* Clear Rx FIFO Overrun Interrupt */
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#define SAICR_TUR (1 << 5) /* Clear Tx FIFO Underrun Interrupt */
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