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@@ -125,7 +125,14 @@
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#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
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#define MTK_PST_DRX_IDX_CFG(x) (MTK_PST_DRX_IDX0 << (x))
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/* PDMA Delay Interrupt Register */
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/* PDMA Delay Interrupt Register */
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-#define MTK_PDMA_DELAY_INT 0xa0c
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+#define MTK_PDMA_DELAY_INT 0xa0c
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+#define MTK_PDMA_DELAY_RX_EN BIT(15)
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+#define MTK_PDMA_DELAY_RX_PINT 4
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+#define MTK_PDMA_DELAY_RX_PINT_SHIFT 8
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+#define MTK_PDMA_DELAY_RX_PTIME 4
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+#define MTK_PDMA_DELAY_RX_DELAY \
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+ (MTK_PDMA_DELAY_RX_EN | MTK_PDMA_DELAY_RX_PTIME | \
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+ (MTK_PDMA_DELAY_RX_PINT << MTK_PDMA_DELAY_RX_PINT_SHIFT))
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/* PDMA Interrupt Status Register */
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/* PDMA Interrupt Status Register */
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#define MTK_PDMA_INT_STATUS 0xa20
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#define MTK_PDMA_INT_STATUS 0xa20
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@@ -206,6 +213,7 @@
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/* QDMA Interrupt Status Register */
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/* QDMA Interrupt Status Register */
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#define MTK_QMTK_INT_STATUS 0x1A18
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#define MTK_QMTK_INT_STATUS 0x1A18
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+#define MTK_RX_DONE_DLY BIT(30)
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#define MTK_RX_DONE_INT3 BIT(19)
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#define MTK_RX_DONE_INT3 BIT(19)
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#define MTK_RX_DONE_INT2 BIT(18)
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#define MTK_RX_DONE_INT2 BIT(18)
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#define MTK_RX_DONE_INT1 BIT(17)
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#define MTK_RX_DONE_INT1 BIT(17)
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@@ -214,8 +222,7 @@
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#define MTK_TX_DONE_INT2 BIT(2)
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#define MTK_TX_DONE_INT2 BIT(2)
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#define MTK_TX_DONE_INT1 BIT(1)
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#define MTK_TX_DONE_INT1 BIT(1)
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#define MTK_TX_DONE_INT0 BIT(0)
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#define MTK_TX_DONE_INT0 BIT(0)
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-#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1 | \
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- MTK_RX_DONE_INT2 | MTK_RX_DONE_INT3)
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+#define MTK_RX_DONE_INT MTK_RX_DONE_DLY
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#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
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#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
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MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
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MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
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