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@@ -304,6 +304,25 @@ static void imx6_pcie_init_phy(struct pcie_port *pp)
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IMX6Q_GPR8_TX_SWING_LOW, 127 << 25);
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}
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+static int imx6_pcie_wait_for_link(struct pcie_port *pp)
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+{
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+ int count = 200;
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+
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+ while (!dw_pcie_link_up(pp)) {
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+ usleep_range(100, 1000);
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+ if (--count)
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+ continue;
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+
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+ dev_err(pp->dev, "phy link never came up\n");
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+ dev_dbg(pp->dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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+ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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+ return -EINVAL;
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+ }
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+
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+ return 0;
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+}
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+
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static void imx6_pcie_host_init(struct pcie_port *pp)
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{
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int count = 0;
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@@ -320,20 +339,7 @@ static void imx6_pcie_host_init(struct pcie_port *pp)
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regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
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IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
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- while (!dw_pcie_link_up(pp)) {
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- usleep_range(100, 1000);
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- count++;
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- if (count >= 200) {
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- dev_err(pp->dev, "phy link never came up\n");
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- dev_dbg(pp->dev,
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- "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
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- readl(pp->dbi_base + PCIE_PHY_DEBUG_R0),
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- readl(pp->dbi_base + PCIE_PHY_DEBUG_R1));
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- break;
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- }
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- }
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-
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- return;
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+ imx6_pcie_wait_for_link(pp);
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}
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static void imx6_pcie_reset_phy(struct pcie_port *pp)
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