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@@ -342,7 +342,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
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ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
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val, !(val & GEN_CMD_FULL), 1000,
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CMD_PKT_STATUS_TIMEOUT_US);
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- if (ret < 0) {
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+ if (ret) {
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dev_err(dsi->dev, "failed to get available command FIFO\n");
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return ret;
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}
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@@ -353,7 +353,7 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val)
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ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
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val, (val & mask) == mask,
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1000, CMD_PKT_STATUS_TIMEOUT_US);
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- if (ret < 0) {
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+ if (ret) {
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dev_err(dsi->dev, "failed to write command FIFO\n");
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return ret;
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}
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@@ -385,7 +385,7 @@ static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi,
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ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS,
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val, !(val & GEN_PLD_W_FULL), 1000,
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CMD_PKT_STATUS_TIMEOUT_US);
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- if (ret < 0) {
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+ if (ret) {
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dev_err(dsi->dev,
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"failed to get available write payload FIFO\n");
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return ret;
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@@ -721,13 +721,13 @@ static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi)
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ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val,
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val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US);
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- if (ret < 0)
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+ if (ret)
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DRM_DEBUG_DRIVER("failed to wait phy lock state\n");
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ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS,
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val, val & PHY_STOP_STATE_CLK_LANE, 1000,
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PHY_STATUS_TIMEOUT_US);
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- if (ret < 0)
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+ if (ret)
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DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n");
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}
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