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@@ -1324,8 +1324,8 @@ static void gfx_v6_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
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amdgpu_ring_write(ring, 0x1);
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amdgpu_ring_write(ring, 0x1);
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}
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}
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-static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
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- u64 seq, unsigned flags)
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+static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
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+ u64 seq, unsigned flags)
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{
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{
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bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
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bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
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bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
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bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
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@@ -1351,17 +1351,9 @@ static void gfx_v6_0_ring_emit_fence_gfx(struct amdgpu_ring *ring, u64 addr,
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amdgpu_ring_write(ring, upper_32_bits(seq));
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amdgpu_ring_write(ring, upper_32_bits(seq));
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}
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}
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-static void gfx_v6_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
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- u64 addr, u64 seq,
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- unsigned flags)
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-{
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- gfx_v6_0_ring_emit_fence_gfx(ring, addr, seq, flags);
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-}
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-
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-
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-static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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- struct amdgpu_ib *ib,
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- unsigned vm_id, bool ctx_switch)
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+static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
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+ struct amdgpu_ib *ib,
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+ unsigned vm_id, bool ctx_switch)
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{
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{
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u32 header, control = 0;
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u32 header, control = 0;
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@@ -1388,13 +1380,6 @@ static void gfx_v6_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
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amdgpu_ring_write(ring, control);
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amdgpu_ring_write(ring, control);
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}
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}
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-static void gfx_v6_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
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- struct amdgpu_ib *ib,
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- unsigned vm_id, bool ctx_switch)
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-{
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- gfx_v6_0_ring_emit_ib_gfx(ring, ib, vm_id, ctx_switch);
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-}
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-
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/**
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/**
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* gfx_v6_0_ring_test_ib - basic ring IB test
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* gfx_v6_0_ring_test_ib - basic ring IB test
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*
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*
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@@ -3119,8 +3104,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_gfx = {
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
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.set_wptr = gfx_v6_0_ring_set_wptr_gfx,
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.parse_cs = NULL,
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.parse_cs = NULL,
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- .emit_ib = gfx_v6_0_ring_emit_ib_gfx,
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- .emit_fence = gfx_v6_0_ring_emit_fence_gfx,
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+ .emit_ib = gfx_v6_0_ring_emit_ib,
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+ .emit_fence = gfx_v6_0_ring_emit_fence,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
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.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
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.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
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.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
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@@ -3136,8 +3121,8 @@ static const struct amdgpu_ring_funcs gfx_v6_0_ring_funcs_compute = {
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.get_wptr = gfx_v6_0_ring_get_wptr,
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.set_wptr = gfx_v6_0_ring_set_wptr_compute,
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.set_wptr = gfx_v6_0_ring_set_wptr_compute,
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.parse_cs = NULL,
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.parse_cs = NULL,
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- .emit_ib = gfx_v6_0_ring_emit_ib_compute,
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- .emit_fence = gfx_v6_0_ring_emit_fence_compute,
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+ .emit_ib = gfx_v6_0_ring_emit_ib,
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+ .emit_fence = gfx_v6_0_ring_emit_fence,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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.emit_pipeline_sync = gfx_v6_0_ring_emit_pipeline_sync,
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.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
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.emit_vm_flush = gfx_v6_0_ring_emit_vm_flush,
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.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
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.emit_gds_switch = gfx_v6_0_ring_emit_gds_switch,
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