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@@ -0,0 +1,1546 @@
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+/*
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+ * Driver for Pondicherry2 memory controller.
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+ *
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+ * Copyright (c) 2016, Intel Corporation.
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+ *
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+ * This program is free software; you can redistribute it and/or modify it
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+ * under the terms and conditions of the GNU General Public License,
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+ * version 2, as published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope it will be useful, but WITHOUT
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+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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+ * more details.
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+ *
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+ * [Derived from sb_edac.c]
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+ *
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+ * Translation of system physical addresses to DIMM addresses
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+ * is a two stage process:
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+ *
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+ * First the Pondicherry 2 memory controller handles slice and channel interleaving
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+ * in "sys2pmi()". This is (almost) completley common between platforms.
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+ *
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+ * Then a platform specific dunit (DIMM unit) completes the process to provide DIMM,
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+ * rank, bank, row and column using the appropriate "dunit_ops" functions/parameters.
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+ */
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+
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+#include <linux/module.h>
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+#include <linux/init.h>
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+#include <linux/pci.h>
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+#include <linux/pci_ids.h>
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+#include <linux/slab.h>
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+#include <linux/delay.h>
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+#include <linux/edac.h>
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+#include <linux/mmzone.h>
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+#include <linux/smp.h>
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+#include <linux/bitmap.h>
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+#include <linux/math64.h>
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+#include <linux/mod_devicetable.h>
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+#include <asm/cpu_device_id.h>
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+#include <asm/intel-family.h>
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+#include <asm/processor.h>
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+#include <asm/mce.h>
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+
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+#include "edac_mc.h"
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+#include "edac_module.h"
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+#include "pnd2_edac.h"
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+
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+#define APL_NUM_CHANNELS 4
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+#define DNV_NUM_CHANNELS 2
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+#define DNV_MAX_DIMMS 2 /* Max DIMMs per channel */
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+
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+enum type {
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+ APL,
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+ DNV, /* All requests go to PMI CH0 on each slice (CH1 disabled) */
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+};
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+
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+struct dram_addr {
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+ int chan;
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+ int dimm;
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+ int rank;
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+ int bank;
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+ int row;
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+ int col;
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+};
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+
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+struct pnd2_pvt {
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+ int dimm_geom[APL_NUM_CHANNELS];
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+ u64 tolm, tohm;
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+};
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+
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+/*
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+ * System address space is divided into multiple regions with
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+ * different interleave rules in each. The as0/as1 regions
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+ * have no interleaving at all. The as2 region is interleaved
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+ * between two channels. The mot region is magic and may overlap
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+ * other regions, with its interleave rules taking precedence.
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+ * Addresses not in any of these regions are interleaved across
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+ * all four channels.
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+ */
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+static struct region {
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+ u64 base;
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+ u64 limit;
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+ u8 enabled;
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+} mot, as0, as1, as2;
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+
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+static struct dunit_ops {
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+ char *name;
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+ enum type type;
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+ int pmiaddr_shift;
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+ int pmiidx_shift;
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+ int channels;
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+ int dimms_per_channel;
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+ int (*rd_reg)(int port, int off, int op, void *data, size_t sz, char *name);
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+ int (*get_registers)(void);
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+ int (*check_ecc)(void);
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+ void (*mk_region)(char *name, struct region *rp, void *asym);
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+ void (*get_dimm_config)(struct mem_ctl_info *mci);
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+ int (*pmi2mem)(struct mem_ctl_info *mci, u64 pmiaddr, u32 pmiidx,
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+ struct dram_addr *daddr, char *msg);
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+} *ops;
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+
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+static struct mem_ctl_info *pnd2_mci;
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+
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+#define PND2_MSG_SIZE 256
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+
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+/* Debug macros */
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+#define pnd2_printk(level, fmt, arg...) \
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+ edac_printk(level, "pnd2", fmt, ##arg)
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+
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+#define pnd2_mc_printk(mci, level, fmt, arg...) \
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+ edac_mc_chipset_printk(mci, level, "pnd2", fmt, ##arg)
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+
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+#define MOT_CHAN_INTLV_BIT_1SLC_2CH 12
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+#define MOT_CHAN_INTLV_BIT_2SLC_2CH 13
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+#define SELECTOR_DISABLED (-1)
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+#define _4GB (1ul << 32)
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+
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+#define PMI_ADDRESS_WIDTH 31
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+#define PND_MAX_PHYS_BIT 39
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+
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+#define APL_ASYMSHIFT 28
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+#define DNV_ASYMSHIFT 31
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+#define CH_HASH_MASK_LSB 6
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+#define SLICE_HASH_MASK_LSB 6
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+#define MOT_SLC_INTLV_BIT 12
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+#define LOG2_PMI_ADDR_GRANULARITY 5
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+#define MOT_SHIFT 24
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+
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+#define GET_BITFIELD(v, lo, hi) (((v) & GENMASK_ULL(hi, lo)) >> (lo))
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+#define U64_LSHIFT(val, s) ((u64)(val) << (s))
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+
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+#ifdef CONFIG_X86_INTEL_SBI_APL
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+#include "linux/platform_data/sbi_apl.h"
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+int sbi_send(int port, int off, int op, u32 *data)
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+{
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+ struct sbi_apl_message sbi_arg;
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+ int ret, read = 0;
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+
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+ memset(&sbi_arg, 0, sizeof(sbi_arg));
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+
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+ if (op == 0 || op == 4 || op == 6)
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+ read = 1;
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+ else
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+ sbi_arg.data = *data;
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+
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+ sbi_arg.opcode = op;
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+ sbi_arg.port_address = port;
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+ sbi_arg.register_offset = off;
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+ ret = sbi_apl_commit(&sbi_arg);
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+ if (ret || sbi_arg.status)
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+ edac_dbg(2, "sbi_send status=%d ret=%d data=%x\n",
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+ sbi_arg.status, ret, sbi_arg.data);
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+
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+ if (ret == 0)
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+ ret = sbi_arg.status;
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+
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+ if (ret == 0 && read)
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+ *data = sbi_arg.data;
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+
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+ return ret;
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+}
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+#else
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+int sbi_send(int port, int off, int op, u32 *data)
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+{
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+ return -EUNATCH;
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+}
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+#endif
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+
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+static int apl_rd_reg(int port, int off, int op, void *data, size_t sz, char *name)
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+{
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+ int ret = 0;
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+
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+ edac_dbg(2, "Read %s port=%x off=%x op=%x\n", name, port, off, op);
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+ switch (sz) {
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+ case 8:
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+ ret = sbi_send(port, off + 4, op, (u32 *)(data + 4));
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+ case 4:
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+ ret = sbi_send(port, off, op, (u32 *)data);
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+ pnd2_printk(KERN_DEBUG, "%s=%x%08x ret=%d\n", name,
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+ sz == 8 ? *((u32 *)(data + 4)) : 0, *((u32 *)data), ret);
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+ break;
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+ }
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+
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+ return ret;
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+}
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+
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+static u64 get_mem_ctrl_hub_base_addr(void)
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+{
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+ struct b_cr_mchbar_lo_pci lo;
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+ struct b_cr_mchbar_hi_pci hi;
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+ struct pci_dev *pdev;
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+
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+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL);
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+ if (pdev) {
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+ pci_read_config_dword(pdev, 0x48, (u32 *)&lo);
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+ pci_read_config_dword(pdev, 0x4c, (u32 *)&hi);
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+ pci_dev_put(pdev);
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+ } else {
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+ return 0;
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+ }
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+
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+ if (!lo.enable) {
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+ edac_dbg(2, "MMIO via memory controller hub base address is disabled!\n");
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+ return 0;
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+ }
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+
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+ return U64_LSHIFT(hi.base, 32) | U64_LSHIFT(lo.base, 15);
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+}
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+
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+static u64 get_sideband_reg_base_addr(void)
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+{
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+ struct pci_dev *pdev;
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+ u32 hi, lo;
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+
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+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x19dd, NULL);
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+ if (pdev) {
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+ pci_read_config_dword(pdev, 0x10, &lo);
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+ pci_read_config_dword(pdev, 0x14, &hi);
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+ pci_dev_put(pdev);
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+ return (U64_LSHIFT(hi, 32) | U64_LSHIFT(lo, 0));
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+ } else {
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+ return 0xfd000000;
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+ }
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+}
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+
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+static int dnv_rd_reg(int port, int off, int op, void *data, size_t sz, char *name)
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+{
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+ struct pci_dev *pdev;
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+ char *base;
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+ u64 addr;
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+
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+ if (op == 4) {
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+ pdev = pci_get_device(PCI_VENDOR_ID_INTEL, 0x1980, NULL);
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+ if (!pdev)
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+ return -ENODEV;
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+
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+ pci_read_config_dword(pdev, off, data);
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+ pci_dev_put(pdev);
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+ } else {
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+ /* MMIO via memory controller hub base address */
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+ if (op == 0 && port == 0x4c) {
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+ addr = get_mem_ctrl_hub_base_addr();
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+ if (!addr)
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+ return -ENODEV;
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+ } else {
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+ /* MMIO via sideband register base address */
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+ addr = get_sideband_reg_base_addr();
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+ if (!addr)
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+ return -ENODEV;
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+ addr += (port << 16);
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+ }
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+
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+ base = ioremap((resource_size_t)addr, 0x10000);
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+ if (!base)
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+ return -ENODEV;
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+
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+ if (sz == 8)
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+ *(u32 *)(data + 4) = *(u32 *)(base + off + 4);
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+ *(u32 *)data = *(u32 *)(base + off);
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+
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+ iounmap(base);
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+ }
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+
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+ edac_dbg(2, "Read %s=%.8x_%.8x\n", name,
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+ (sz == 8) ? *(u32 *)(data + 4) : 0, *(u32 *)data);
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+
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+ return 0;
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+}
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+
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+#define RD_REGP(regp, regname, port) \
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+ ops->rd_reg(port, \
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+ regname##_offset, \
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+ regname##_r_opcode, \
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+ regp, sizeof(struct regname), \
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+ #regname)
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+
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+#define RD_REG(regp, regname) \
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+ ops->rd_reg(regname ## _port, \
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+ regname##_offset, \
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+ regname##_r_opcode, \
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+ regp, sizeof(struct regname), \
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+ #regname)
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+
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+static u64 top_lm, top_hm;
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+static bool two_slices;
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+static bool two_channels; /* Both PMI channels in one slice enabled */
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+
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+static u8 sym_chan_mask;
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+static u8 asym_chan_mask;
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+static u8 chan_mask;
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+
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+static int slice_selector = -1;
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+static int chan_selector = -1;
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+static u64 slice_hash_mask;
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+static u64 chan_hash_mask;
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+
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+static void mk_region(char *name, struct region *rp, u64 base, u64 limit)
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+{
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+ rp->enabled = 1;
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+ rp->base = base;
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+ rp->limit = limit;
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+ edac_dbg(2, "Region:%s [%llx, %llx]\n", name, base, limit);
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+}
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+
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+static void mk_region_mask(char *name, struct region *rp, u64 base, u64 mask)
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+{
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+ if (mask == 0) {
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+ pr_info(FW_BUG "MOT mask cannot be zero\n");
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+ return;
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+ }
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+ if (mask != GENMASK_ULL(PND_MAX_PHYS_BIT, __ffs(mask))) {
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+ pr_info(FW_BUG "MOT mask not power of two\n");
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+ return;
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+ }
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+ if (base & ~mask) {
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+ pr_info(FW_BUG "MOT region base/mask alignment error\n");
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+ return;
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+ }
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+ rp->base = base;
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+ rp->limit = (base | ~mask) & GENMASK_ULL(PND_MAX_PHYS_BIT, 0);
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+ rp->enabled = 1;
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+ edac_dbg(2, "Region:%s [%llx, %llx]\n", name, base, rp->limit);
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+}
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+
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+static bool in_region(struct region *rp, u64 addr)
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+{
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+ if (!rp->enabled)
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+ return false;
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+
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+ return rp->base <= addr && addr <= rp->limit;
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+}
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+
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+static int gen_sym_mask(struct b_cr_slice_channel_hash *p)
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+{
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+ int mask = 0;
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+
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+ if (!p->slice_0_mem_disabled)
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+ mask |= p->sym_slice0_channel_enabled;
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+
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+ if (!p->slice_1_disabled)
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+ mask |= p->sym_slice1_channel_enabled << 2;
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+
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+ if (p->ch_1_disabled || p->enable_pmi_dual_data_mode)
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+ mask &= 0x5;
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+
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+ return mask;
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+}
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+
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+static int gen_asym_mask(struct b_cr_slice_channel_hash *p,
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+ struct b_cr_asym_mem_region0_mchbar *as0,
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+ struct b_cr_asym_mem_region1_mchbar *as1,
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+ struct b_cr_asym_2way_mem_region_mchbar *as2way)
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+{
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+ const int intlv[] = { 0x5, 0xA, 0x3, 0xC };
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+ int mask = 0;
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+
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+ if (as2way->asym_2way_interleave_enable)
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+ mask = intlv[as2way->asym_2way_intlv_mode];
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+ if (as0->slice0_asym_enable)
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+ mask |= (1 << as0->slice0_asym_channel_select);
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+ if (as1->slice1_asym_enable)
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+ mask |= (4 << as1->slice1_asym_channel_select);
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+ if (p->slice_0_mem_disabled)
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+ mask &= 0xc;
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+ if (p->slice_1_disabled)
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+ mask &= 0x3;
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+ if (p->ch_1_disabled || p->enable_pmi_dual_data_mode)
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+ mask &= 0x5;
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+
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+ return mask;
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+}
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+
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+static struct b_cr_tolud_pci tolud;
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+static struct b_cr_touud_lo_pci touud_lo;
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+static struct b_cr_touud_hi_pci touud_hi;
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+static struct b_cr_asym_mem_region0_mchbar asym0;
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+static struct b_cr_asym_mem_region1_mchbar asym1;
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+static struct b_cr_asym_2way_mem_region_mchbar asym_2way;
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+static struct b_cr_mot_out_base_mchbar mot_base;
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+static struct b_cr_mot_out_mask_mchbar mot_mask;
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+static struct b_cr_slice_channel_hash chash;
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+
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+/* Apollo Lake dunit */
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+/*
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+ * Validated on board with just two DIMMs in the [0] and [2] positions
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+ * in this array. Other port number matches documentation, but caution
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+ * advised.
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+ */
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+static const int apl_dports[APL_NUM_CHANNELS] = { 0x18, 0x10, 0x11, 0x19 };
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+static struct d_cr_drp0 drp0[APL_NUM_CHANNELS];
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+
|
|
|
+/* Denverton dunit */
|
|
|
+static const int dnv_dports[DNV_NUM_CHANNELS] = { 0x10, 0x12 };
|
|
|
+static struct d_cr_dsch dsch;
|
|
|
+static struct d_cr_ecc_ctrl ecc_ctrl[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_drp drp[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap dmap[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap1 dmap1[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap2 dmap2[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap3 dmap3[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap4 dmap4[DNV_NUM_CHANNELS];
|
|
|
+static struct d_cr_dmap5 dmap5[DNV_NUM_CHANNELS];
|
|
|
+
|
|
|
+static void apl_mk_region(char *name, struct region *rp, void *asym)
|
|
|
+{
|
|
|
+ struct b_cr_asym_mem_region0_mchbar *a = asym;
|
|
|
+
|
|
|
+ mk_region(name, rp,
|
|
|
+ U64_LSHIFT(a->slice0_asym_base, APL_ASYMSHIFT),
|
|
|
+ U64_LSHIFT(a->slice0_asym_limit, APL_ASYMSHIFT) +
|
|
|
+ GENMASK_ULL(APL_ASYMSHIFT - 1, 0));
|
|
|
+}
|
|
|
+
|
|
|
+static void dnv_mk_region(char *name, struct region *rp, void *asym)
|
|
|
+{
|
|
|
+ struct b_cr_asym_mem_region_denverton *a = asym;
|
|
|
+
|
|
|
+ mk_region(name, rp,
|
|
|
+ U64_LSHIFT(a->slice_asym_base, DNV_ASYMSHIFT),
|
|
|
+ U64_LSHIFT(a->slice_asym_limit, DNV_ASYMSHIFT) +
|
|
|
+ GENMASK_ULL(DNV_ASYMSHIFT - 1, 0));
|
|
|
+}
|
|
|
+
|
|
|
+static int apl_get_registers(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (RD_REG(&asym_2way, b_cr_asym_2way_mem_region_mchbar))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ for (i = 0; i < APL_NUM_CHANNELS; i++)
|
|
|
+ if (RD_REGP(&drp0[i], d_cr_drp0, apl_dports[i]))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int dnv_get_registers(void)
|
|
|
+{
|
|
|
+ int i;
|
|
|
+
|
|
|
+ if (RD_REG(&dsch, d_cr_dsch))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ for (i = 0; i < DNV_NUM_CHANNELS; i++)
|
|
|
+ if (RD_REGP(&ecc_ctrl[i], d_cr_ecc_ctrl, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&drp[i], d_cr_drp, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap[i], d_cr_dmap, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap1[i], d_cr_dmap1, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap2[i], d_cr_dmap2, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap3[i], d_cr_dmap3, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap4[i], d_cr_dmap4, dnv_dports[i]) ||
|
|
|
+ RD_REGP(&dmap5[i], d_cr_dmap5, dnv_dports[i]))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Read all the h/w config registers once here (they don't
|
|
|
+ * change at run time. Figure out which address ranges have
|
|
|
+ * which interleave characteristics.
|
|
|
+ */
|
|
|
+static int get_registers(void)
|
|
|
+{
|
|
|
+ const int intlv[] = { 10, 11, 12, 12 };
|
|
|
+
|
|
|
+ if (RD_REG(&tolud, b_cr_tolud_pci) ||
|
|
|
+ RD_REG(&touud_lo, b_cr_touud_lo_pci) ||
|
|
|
+ RD_REG(&touud_hi, b_cr_touud_hi_pci) ||
|
|
|
+ RD_REG(&asym0, b_cr_asym_mem_region0_mchbar) ||
|
|
|
+ RD_REG(&asym1, b_cr_asym_mem_region1_mchbar) ||
|
|
|
+ RD_REG(&mot_base, b_cr_mot_out_base_mchbar) ||
|
|
|
+ RD_REG(&mot_mask, b_cr_mot_out_mask_mchbar) ||
|
|
|
+ RD_REG(&chash, b_cr_slice_channel_hash))
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ if (ops->get_registers())
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ if (ops->type == DNV) {
|
|
|
+ /* PMI channel idx (always 0) for asymmetric region */
|
|
|
+ asym0.slice0_asym_channel_select = 0;
|
|
|
+ asym1.slice1_asym_channel_select = 0;
|
|
|
+ /* PMI channel bitmap (always 1) for symmetric region */
|
|
|
+ chash.sym_slice0_channel_enabled = 0x1;
|
|
|
+ chash.sym_slice1_channel_enabled = 0x1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (asym0.slice0_asym_enable)
|
|
|
+ ops->mk_region("as0", &as0, &asym0);
|
|
|
+
|
|
|
+ if (asym1.slice1_asym_enable)
|
|
|
+ ops->mk_region("as1", &as1, &asym1);
|
|
|
+
|
|
|
+ if (asym_2way.asym_2way_interleave_enable) {
|
|
|
+ mk_region("as2way", &as2,
|
|
|
+ U64_LSHIFT(asym_2way.asym_2way_base, APL_ASYMSHIFT),
|
|
|
+ U64_LSHIFT(asym_2way.asym_2way_limit, APL_ASYMSHIFT) +
|
|
|
+ GENMASK_ULL(APL_ASYMSHIFT - 1, 0));
|
|
|
+ }
|
|
|
+
|
|
|
+ if (mot_base.imr_en) {
|
|
|
+ mk_region_mask("mot", &mot,
|
|
|
+ U64_LSHIFT(mot_base.mot_out_base, MOT_SHIFT),
|
|
|
+ U64_LSHIFT(mot_mask.mot_out_mask, MOT_SHIFT));
|
|
|
+ }
|
|
|
+
|
|
|
+ top_lm = U64_LSHIFT(tolud.tolud, 20);
|
|
|
+ top_hm = U64_LSHIFT(touud_hi.touud, 32) | U64_LSHIFT(touud_lo.touud, 20);
|
|
|
+
|
|
|
+ two_slices = !chash.slice_1_disabled &&
|
|
|
+ !chash.slice_0_mem_disabled &&
|
|
|
+ (chash.sym_slice0_channel_enabled != 0) &&
|
|
|
+ (chash.sym_slice1_channel_enabled != 0);
|
|
|
+ two_channels = !chash.ch_1_disabled &&
|
|
|
+ !chash.enable_pmi_dual_data_mode &&
|
|
|
+ ((chash.sym_slice0_channel_enabled == 3) ||
|
|
|
+ (chash.sym_slice1_channel_enabled == 3));
|
|
|
+
|
|
|
+ sym_chan_mask = gen_sym_mask(&chash);
|
|
|
+ asym_chan_mask = gen_asym_mask(&chash, &asym0, &asym1, &asym_2way);
|
|
|
+ chan_mask = sym_chan_mask | asym_chan_mask;
|
|
|
+
|
|
|
+ if (two_slices && !two_channels) {
|
|
|
+ if (chash.hvm_mode)
|
|
|
+ slice_selector = 29;
|
|
|
+ else
|
|
|
+ slice_selector = intlv[chash.interleave_mode];
|
|
|
+ } else if (!two_slices && two_channels) {
|
|
|
+ if (chash.hvm_mode)
|
|
|
+ chan_selector = 29;
|
|
|
+ else
|
|
|
+ chan_selector = intlv[chash.interleave_mode];
|
|
|
+ } else if (two_slices && two_channels) {
|
|
|
+ if (chash.hvm_mode) {
|
|
|
+ slice_selector = 29;
|
|
|
+ chan_selector = 30;
|
|
|
+ } else {
|
|
|
+ slice_selector = intlv[chash.interleave_mode];
|
|
|
+ chan_selector = intlv[chash.interleave_mode] + 1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ if (two_slices) {
|
|
|
+ if (!chash.hvm_mode)
|
|
|
+ slice_hash_mask = chash.slice_hash_mask << SLICE_HASH_MASK_LSB;
|
|
|
+ if (!two_channels)
|
|
|
+ slice_hash_mask |= BIT_ULL(slice_selector);
|
|
|
+ }
|
|
|
+
|
|
|
+ if (two_channels) {
|
|
|
+ if (!chash.hvm_mode)
|
|
|
+ chan_hash_mask = chash.ch_hash_mask << CH_HASH_MASK_LSB;
|
|
|
+ if (!two_slices)
|
|
|
+ chan_hash_mask |= BIT_ULL(chan_selector);
|
|
|
+ }
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/* Get a contiguous memory address (remove the MMIO gap) */
|
|
|
+static u64 remove_mmio_gap(u64 sys)
|
|
|
+{
|
|
|
+ return (sys < _4GB) ? sys : sys - (_4GB - top_lm);
|
|
|
+}
|
|
|
+
|
|
|
+/* Squeeze out one address bit, shift upper part down to fill gap */
|
|
|
+static void remove_addr_bit(u64 *addr, int bitidx)
|
|
|
+{
|
|
|
+ u64 mask;
|
|
|
+
|
|
|
+ if (bitidx == -1)
|
|
|
+ return;
|
|
|
+
|
|
|
+ mask = (1ull << bitidx) - 1;
|
|
|
+ *addr = ((*addr >> 1) & ~mask) | (*addr & mask);
|
|
|
+}
|
|
|
+
|
|
|
+/* XOR all the bits from addr specified in mask */
|
|
|
+static int hash_by_mask(u64 addr, u64 mask)
|
|
|
+{
|
|
|
+ u64 result = addr & mask;
|
|
|
+
|
|
|
+ result = (result >> 32) ^ result;
|
|
|
+ result = (result >> 16) ^ result;
|
|
|
+ result = (result >> 8) ^ result;
|
|
|
+ result = (result >> 4) ^ result;
|
|
|
+ result = (result >> 2) ^ result;
|
|
|
+ result = (result >> 1) ^ result;
|
|
|
+
|
|
|
+ return (int)result & 1;
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * First stage decode. Take the system address and figure out which
|
|
|
+ * second stage will deal with it based on interleave modes.
|
|
|
+ */
|
|
|
+static int sys2pmi(const u64 addr, u32 *pmiidx, u64 *pmiaddr, char *msg)
|
|
|
+{
|
|
|
+ u64 contig_addr, contig_base, contig_offset, contig_base_adj;
|
|
|
+ int mot_intlv_bit = two_slices ? MOT_CHAN_INTLV_BIT_2SLC_2CH :
|
|
|
+ MOT_CHAN_INTLV_BIT_1SLC_2CH;
|
|
|
+ int slice_intlv_bit_rm = SELECTOR_DISABLED;
|
|
|
+ int chan_intlv_bit_rm = SELECTOR_DISABLED;
|
|
|
+ /* Determine if address is in the MOT region. */
|
|
|
+ bool mot_hit = in_region(&mot, addr);
|
|
|
+ /* Calculate the number of symmetric regions enabled. */
|
|
|
+ int sym_channels = hweight8(sym_chan_mask);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * The amount we need to shift the asym base can be determined by the
|
|
|
+ * number of enabled symmetric channels.
|
|
|
+ * NOTE: This can only work because symmetric memory is not supposed
|
|
|
+ * to do a 3-way interleave.
|
|
|
+ */
|
|
|
+ int sym_chan_shift = sym_channels >> 1;
|
|
|
+
|
|
|
+ /* Give up if address is out of range, or in MMIO gap */
|
|
|
+ if (addr >= (1ul << PND_MAX_PHYS_BIT) ||
|
|
|
+ (addr >= top_lm && addr < _4GB) || addr >= top_hm) {
|
|
|
+ snprintf(msg, PND2_MSG_SIZE, "Error address 0x%llx is not DRAM", addr);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Get a contiguous memory address (remove the MMIO gap) */
|
|
|
+ contig_addr = remove_mmio_gap(addr);
|
|
|
+
|
|
|
+ if (in_region(&as0, addr)) {
|
|
|
+ *pmiidx = asym0.slice0_asym_channel_select;
|
|
|
+
|
|
|
+ contig_base = remove_mmio_gap(as0.base);
|
|
|
+ contig_offset = contig_addr - contig_base;
|
|
|
+ contig_base_adj = (contig_base >> sym_chan_shift) *
|
|
|
+ ((chash.sym_slice0_channel_enabled >> (*pmiidx & 1)) & 1);
|
|
|
+ contig_addr = contig_offset + ((sym_channels > 0) ? contig_base_adj : 0ull);
|
|
|
+ } else if (in_region(&as1, addr)) {
|
|
|
+ *pmiidx = 2u + asym1.slice1_asym_channel_select;
|
|
|
+
|
|
|
+ contig_base = remove_mmio_gap(as1.base);
|
|
|
+ contig_offset = contig_addr - contig_base;
|
|
|
+ contig_base_adj = (contig_base >> sym_chan_shift) *
|
|
|
+ ((chash.sym_slice1_channel_enabled >> (*pmiidx & 1)) & 1);
|
|
|
+ contig_addr = contig_offset + ((sym_channels > 0) ? contig_base_adj : 0ull);
|
|
|
+ } else if (in_region(&as2, addr) && (asym_2way.asym_2way_intlv_mode == 0x3ul)) {
|
|
|
+ bool channel1;
|
|
|
+
|
|
|
+ mot_intlv_bit = MOT_CHAN_INTLV_BIT_1SLC_2CH;
|
|
|
+ *pmiidx = (asym_2way.asym_2way_intlv_mode & 1) << 1;
|
|
|
+ channel1 = mot_hit ? ((bool)((addr >> mot_intlv_bit) & 1)) :
|
|
|
+ hash_by_mask(contig_addr, chan_hash_mask);
|
|
|
+ *pmiidx |= (u32)channel1;
|
|
|
+
|
|
|
+ contig_base = remove_mmio_gap(as2.base);
|
|
|
+ chan_intlv_bit_rm = mot_hit ? mot_intlv_bit : chan_selector;
|
|
|
+ contig_offset = contig_addr - contig_base;
|
|
|
+ remove_addr_bit(&contig_offset, chan_intlv_bit_rm);
|
|
|
+ contig_addr = (contig_base >> sym_chan_shift) + contig_offset;
|
|
|
+ } else {
|
|
|
+ /* Otherwise we're in normal, boring symmetric mode. */
|
|
|
+ *pmiidx = 0u;
|
|
|
+
|
|
|
+ if (two_slices) {
|
|
|
+ bool slice1;
|
|
|
+
|
|
|
+ if (mot_hit) {
|
|
|
+ slice_intlv_bit_rm = MOT_SLC_INTLV_BIT;
|
|
|
+ slice1 = (addr >> MOT_SLC_INTLV_BIT) & 1;
|
|
|
+ } else {
|
|
|
+ slice_intlv_bit_rm = slice_selector;
|
|
|
+ slice1 = hash_by_mask(addr, slice_hash_mask);
|
|
|
+ }
|
|
|
+
|
|
|
+ *pmiidx = (u32)slice1 << 1;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (two_channels) {
|
|
|
+ bool channel1;
|
|
|
+
|
|
|
+ mot_intlv_bit = two_slices ? MOT_CHAN_INTLV_BIT_2SLC_2CH :
|
|
|
+ MOT_CHAN_INTLV_BIT_1SLC_2CH;
|
|
|
+
|
|
|
+ if (mot_hit) {
|
|
|
+ chan_intlv_bit_rm = mot_intlv_bit;
|
|
|
+ channel1 = (addr >> mot_intlv_bit) & 1;
|
|
|
+ } else {
|
|
|
+ chan_intlv_bit_rm = chan_selector;
|
|
|
+ channel1 = hash_by_mask(contig_addr, chan_hash_mask);
|
|
|
+ }
|
|
|
+
|
|
|
+ *pmiidx |= (u32)channel1;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Remove the chan_selector bit first */
|
|
|
+ remove_addr_bit(&contig_addr, chan_intlv_bit_rm);
|
|
|
+ /* Remove the slice bit (we remove it second because it must be lower */
|
|
|
+ remove_addr_bit(&contig_addr, slice_intlv_bit_rm);
|
|
|
+ *pmiaddr = contig_addr;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/* Translate PMI address to memory (rank, row, bank, column) */
|
|
|
+#define C(n) (0x10 | (n)) /* column */
|
|
|
+#define B(n) (0x20 | (n)) /* bank */
|
|
|
+#define R(n) (0x40 | (n)) /* row */
|
|
|
+#define RS (0x80) /* rank */
|
|
|
+
|
|
|
+/* addrdec values */
|
|
|
+#define AMAP_1KB 0
|
|
|
+#define AMAP_2KB 1
|
|
|
+#define AMAP_4KB 2
|
|
|
+#define AMAP_RSVD 3
|
|
|
+
|
|
|
+/* dden values */
|
|
|
+#define DEN_4Gb 0
|
|
|
+#define DEN_8Gb 2
|
|
|
+
|
|
|
+/* dwid values */
|
|
|
+#define X8 0
|
|
|
+#define X16 1
|
|
|
+
|
|
|
+static struct dimm_geometry {
|
|
|
+ u8 addrdec;
|
|
|
+ u8 dden;
|
|
|
+ u8 dwid;
|
|
|
+ u8 rowbits, colbits;
|
|
|
+ u16 bits[PMI_ADDRESS_WIDTH];
|
|
|
+} dimms[] = {
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_1KB, .dden = DEN_4Gb, .dwid = X16,
|
|
|
+ .rowbits = 15, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0),
|
|
|
+ R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9),
|
|
|
+ R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ 0, 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_1KB, .dden = DEN_4Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0),
|
|
|
+ R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9),
|
|
|
+ R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_1KB, .dden = DEN_8Gb, .dwid = X16,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0),
|
|
|
+ R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9),
|
|
|
+ R(10), C(7), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_1KB, .dden = DEN_8Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 11,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), B(0), B(1), B(2), R(0),
|
|
|
+ R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8), R(9),
|
|
|
+ R(10), C(7), C(8), C(9), R(11), RS, C(11), R(12), R(13),
|
|
|
+ R(14), R(15), 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_2KB, .dden = DEN_4Gb, .dwid = X16,
|
|
|
+ .rowbits = 15, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2),
|
|
|
+ R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8),
|
|
|
+ R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ 0, 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_2KB, .dden = DEN_4Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2),
|
|
|
+ R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8),
|
|
|
+ R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_2KB, .dden = DEN_8Gb, .dwid = X16,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2),
|
|
|
+ R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8),
|
|
|
+ R(9), R(10), C(8), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_2KB, .dden = DEN_8Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 11,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), B(0), B(1), B(2),
|
|
|
+ R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7), R(8),
|
|
|
+ R(9), R(10), C(8), C(9), R(11), RS, C(11), R(12), R(13),
|
|
|
+ R(14), R(15), 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_4KB, .dden = DEN_4Gb, .dwid = X16,
|
|
|
+ .rowbits = 15, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1),
|
|
|
+ B(2), R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
|
|
|
+ R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ 0, 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_4KB, .dden = DEN_4Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1),
|
|
|
+ B(2), R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
|
|
|
+ R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_4KB, .dden = DEN_8Gb, .dwid = X16,
|
|
|
+ .rowbits = 16, .colbits = 10,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1),
|
|
|
+ B(2), R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
|
|
|
+ R(8), R(9), R(10), C(9), R(11), RS, R(12), R(13), R(14),
|
|
|
+ R(15), 0, 0, 0
|
|
|
+ }
|
|
|
+ },
|
|
|
+ {
|
|
|
+ .addrdec = AMAP_4KB, .dden = DEN_8Gb, .dwid = X8,
|
|
|
+ .rowbits = 16, .colbits = 11,
|
|
|
+ .bits = {
|
|
|
+ C(2), C(3), C(4), C(5), C(6), C(7), C(8), B(0), B(1),
|
|
|
+ B(2), R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
|
|
|
+ R(8), R(9), R(10), C(9), R(11), RS, C(11), R(12), R(13),
|
|
|
+ R(14), R(15), 0, 0
|
|
|
+ }
|
|
|
+ }
|
|
|
+};
|
|
|
+
|
|
|
+static int bank_hash(u64 pmiaddr, int idx, int shft)
|
|
|
+{
|
|
|
+ int bhash = 0;
|
|
|
+
|
|
|
+ switch (idx) {
|
|
|
+ case 0:
|
|
|
+ bhash ^= ((pmiaddr >> (12 + shft)) ^ (pmiaddr >> (9 + shft))) & 1;
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ bhash ^= (((pmiaddr >> (10 + shft)) ^ (pmiaddr >> (8 + shft))) & 1) << 1;
|
|
|
+ bhash ^= ((pmiaddr >> 22) & 1) << 1;
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ bhash ^= (((pmiaddr >> (13 + shft)) ^ (pmiaddr >> (11 + shft))) & 1) << 2;
|
|
|
+ break;
|
|
|
+ }
|
|
|
+
|
|
|
+ return bhash;
|
|
|
+}
|
|
|
+
|
|
|
+static int rank_hash(u64 pmiaddr)
|
|
|
+{
|
|
|
+ return ((pmiaddr >> 16) ^ (pmiaddr >> 10)) & 1;
|
|
|
+}
|
|
|
+
|
|
|
+/* Second stage decode. Compute rank, bank, row & column. */
|
|
|
+static int apl_pmi2mem(struct mem_ctl_info *mci, u64 pmiaddr, u32 pmiidx,
|
|
|
+ struct dram_addr *daddr, char *msg)
|
|
|
+{
|
|
|
+ struct d_cr_drp0 *cr_drp0 = &drp0[pmiidx];
|
|
|
+ struct pnd2_pvt *pvt = mci->pvt_info;
|
|
|
+ int g = pvt->dimm_geom[pmiidx];
|
|
|
+ struct dimm_geometry *d = &dimms[g];
|
|
|
+ int column = 0, bank = 0, row = 0, rank = 0;
|
|
|
+ int i, idx, type, skiprs = 0;
|
|
|
+
|
|
|
+ for (i = 0; i < PMI_ADDRESS_WIDTH; i++) {
|
|
|
+ int bit = (pmiaddr >> i) & 1;
|
|
|
+
|
|
|
+ if (i + skiprs >= PMI_ADDRESS_WIDTH) {
|
|
|
+ snprintf(msg, PND2_MSG_SIZE, "Bad dimm_geometry[] table\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ type = d->bits[i + skiprs] & ~0xf;
|
|
|
+ idx = d->bits[i + skiprs] & 0xf;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * On single rank DIMMs ignore the rank select bit
|
|
|
+ * and shift remainder of "bits[]" down one place.
|
|
|
+ */
|
|
|
+ if (type == RS && (cr_drp0->rken0 + cr_drp0->rken1) == 1) {
|
|
|
+ skiprs = 1;
|
|
|
+ type = d->bits[i + skiprs] & ~0xf;
|
|
|
+ idx = d->bits[i + skiprs] & 0xf;
|
|
|
+ }
|
|
|
+
|
|
|
+ switch (type) {
|
|
|
+ case C(0):
|
|
|
+ column |= (bit << idx);
|
|
|
+ break;
|
|
|
+ case B(0):
|
|
|
+ bank |= (bit << idx);
|
|
|
+ if (cr_drp0->bahen)
|
|
|
+ bank ^= bank_hash(pmiaddr, idx, d->addrdec);
|
|
|
+ break;
|
|
|
+ case R(0):
|
|
|
+ row |= (bit << idx);
|
|
|
+ break;
|
|
|
+ case RS:
|
|
|
+ rank = bit;
|
|
|
+ if (cr_drp0->rsien)
|
|
|
+ rank ^= rank_hash(pmiaddr);
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ if (bit) {
|
|
|
+ snprintf(msg, PND2_MSG_SIZE, "Bad translation\n");
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+ goto done;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+done:
|
|
|
+ daddr->col = column;
|
|
|
+ daddr->bank = bank;
|
|
|
+ daddr->row = row;
|
|
|
+ daddr->rank = rank;
|
|
|
+ daddr->dimm = 0;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+/* Pluck bit "in" from pmiaddr and return value shifted to bit "out" */
|
|
|
+#define dnv_get_bit(pmi, in, out) ((int)(((pmi) >> (in)) & 1u) << (out))
|
|
|
+
|
|
|
+static int dnv_pmi2mem(struct mem_ctl_info *mci, u64 pmiaddr, u32 pmiidx,
|
|
|
+ struct dram_addr *daddr, char *msg)
|
|
|
+{
|
|
|
+ /* Rank 0 or 1 */
|
|
|
+ daddr->rank = dnv_get_bit(pmiaddr, dmap[pmiidx].rs0 + 13, 0);
|
|
|
+ /* Rank 2 or 3 */
|
|
|
+ daddr->rank |= dnv_get_bit(pmiaddr, dmap[pmiidx].rs1 + 13, 1);
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Normally ranks 0,1 are DIMM0, and 2,3 are DIMM1, but we
|
|
|
+ * flip them if DIMM1 is larger than DIMM0.
|
|
|
+ */
|
|
|
+ daddr->dimm = (daddr->rank >= 2) ^ drp[pmiidx].dimmflip;
|
|
|
+
|
|
|
+ daddr->bank = dnv_get_bit(pmiaddr, dmap[pmiidx].ba0 + 6, 0);
|
|
|
+ daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].ba1 + 6, 1);
|
|
|
+ daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg0 + 6, 2);
|
|
|
+ if (dsch.ddr4en)
|
|
|
+ daddr->bank |= dnv_get_bit(pmiaddr, dmap[pmiidx].bg1 + 6, 3);
|
|
|
+ if (dmap1[pmiidx].bxor) {
|
|
|
+ if (dsch.ddr4en) {
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 0);
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 1);
|
|
|
+ if (dsch.chan_width == 0)
|
|
|
+ /* 64/72 bit dram channel width */
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2);
|
|
|
+ else
|
|
|
+ /* 32/40 bit dram channel width */
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2);
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 3);
|
|
|
+ } else {
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 0);
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 1);
|
|
|
+ if (dsch.chan_width == 0)
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 2);
|
|
|
+ else
|
|
|
+ daddr->bank ^= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 2);
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ daddr->row = dnv_get_bit(pmiaddr, dmap2[pmiidx].row0 + 6, 0);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row1 + 6, 1);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row2 + 6, 2);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row3 + 6, 3);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row4 + 6, 4);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap2[pmiidx].row5 + 6, 5);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row6 + 6, 6);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row7 + 6, 7);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row8 + 6, 8);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row9 + 6, 9);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row10 + 6, 10);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap3[pmiidx].row11 + 6, 11);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row12 + 6, 12);
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row13 + 6, 13);
|
|
|
+ if (dmap4[pmiidx].row14 != 31)
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row14 + 6, 14);
|
|
|
+ if (dmap4[pmiidx].row15 != 31)
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row15 + 6, 15);
|
|
|
+ if (dmap4[pmiidx].row16 != 31)
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row16 + 6, 16);
|
|
|
+ if (dmap4[pmiidx].row17 != 31)
|
|
|
+ daddr->row |= dnv_get_bit(pmiaddr, dmap4[pmiidx].row17 + 6, 17);
|
|
|
+
|
|
|
+ daddr->col = dnv_get_bit(pmiaddr, dmap5[pmiidx].ca3 + 6, 3);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca4 + 6, 4);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca5 + 6, 5);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca6 + 6, 6);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca7 + 6, 7);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca8 + 6, 8);
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap5[pmiidx].ca9 + 6, 9);
|
|
|
+ if (!dsch.ddr4en && dmap1[pmiidx].ca11 != 0x3f)
|
|
|
+ daddr->col |= dnv_get_bit(pmiaddr, dmap1[pmiidx].ca11 + 13, 11);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int check_channel(int ch)
|
|
|
+{
|
|
|
+ if (drp0[ch].dramtype != 0) {
|
|
|
+ pnd2_printk(KERN_INFO, "Unsupported DIMM in channel %d\n", ch);
|
|
|
+ return 1;
|
|
|
+ } else if (drp0[ch].eccen == 0) {
|
|
|
+ pnd2_printk(KERN_INFO, "ECC disabled on channel %d\n", ch);
|
|
|
+ return 1;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int apl_check_ecc_active(void)
|
|
|
+{
|
|
|
+ int i, ret = 0;
|
|
|
+
|
|
|
+ /* Check dramtype and ECC mode for each present DIMM */
|
|
|
+ for (i = 0; i < APL_NUM_CHANNELS; i++)
|
|
|
+ if (chan_mask & BIT(i))
|
|
|
+ ret += check_channel(i);
|
|
|
+ return ret ? -EINVAL : 0;
|
|
|
+}
|
|
|
+
|
|
|
+#define DIMMS_PRESENT(d) ((d)->rken0 + (d)->rken1 + (d)->rken2 + (d)->rken3)
|
|
|
+
|
|
|
+static int check_unit(int ch)
|
|
|
+{
|
|
|
+ struct d_cr_drp *d = &drp[ch];
|
|
|
+
|
|
|
+ if (DIMMS_PRESENT(d) && !ecc_ctrl[ch].eccen) {
|
|
|
+ pnd2_printk(KERN_INFO, "ECC disabled on channel %d\n", ch);
|
|
|
+ return 1;
|
|
|
+ }
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int dnv_check_ecc_active(void)
|
|
|
+{
|
|
|
+ int i, ret = 0;
|
|
|
+
|
|
|
+ for (i = 0; i < DNV_NUM_CHANNELS; i++)
|
|
|
+ ret += check_unit(i);
|
|
|
+ return ret ? -EINVAL : 0;
|
|
|
+}
|
|
|
+
|
|
|
+static int get_memory_error_data(struct mem_ctl_info *mci, u64 addr,
|
|
|
+ struct dram_addr *daddr, char *msg)
|
|
|
+{
|
|
|
+ u64 pmiaddr;
|
|
|
+ u32 pmiidx;
|
|
|
+ int ret;
|
|
|
+
|
|
|
+ ret = sys2pmi(addr, &pmiidx, &pmiaddr, msg);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ pmiaddr >>= ops->pmiaddr_shift;
|
|
|
+ /* pmi channel idx to dimm channel idx */
|
|
|
+ pmiidx >>= ops->pmiidx_shift;
|
|
|
+ daddr->chan = pmiidx;
|
|
|
+
|
|
|
+ ret = ops->pmi2mem(mci, pmiaddr, pmiidx, daddr, msg);
|
|
|
+ if (ret)
|
|
|
+ return ret;
|
|
|
+
|
|
|
+ edac_dbg(0, "SysAddr=%llx PmiAddr=%llx Channel=%d DIMM=%d Rank=%d Bank=%d Row=%d Column=%d\n",
|
|
|
+ addr, pmiaddr, daddr->chan, daddr->dimm, daddr->rank, daddr->bank, daddr->row, daddr->col);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void pnd2_mce_output_error(struct mem_ctl_info *mci, const struct mce *m,
|
|
|
+ struct dram_addr *daddr)
|
|
|
+{
|
|
|
+ enum hw_event_mc_err_type tp_event;
|
|
|
+ char *optype, msg[PND2_MSG_SIZE];
|
|
|
+ bool ripv = m->mcgstatus & MCG_STATUS_RIPV;
|
|
|
+ bool overflow = m->status & MCI_STATUS_OVER;
|
|
|
+ bool uc_err = m->status & MCI_STATUS_UC;
|
|
|
+ bool recov = m->status & MCI_STATUS_S;
|
|
|
+ u32 core_err_cnt = GET_BITFIELD(m->status, 38, 52);
|
|
|
+ u32 mscod = GET_BITFIELD(m->status, 16, 31);
|
|
|
+ u32 errcode = GET_BITFIELD(m->status, 0, 15);
|
|
|
+ u32 optypenum = GET_BITFIELD(m->status, 4, 6);
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ tp_event = uc_err ? (ripv ? HW_EVENT_ERR_FATAL : HW_EVENT_ERR_UNCORRECTED) :
|
|
|
+ HW_EVENT_ERR_CORRECTED;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * According with Table 15-9 of the Intel Architecture spec vol 3A,
|
|
|
+ * memory errors should fit in this mask:
|
|
|
+ * 000f 0000 1mmm cccc (binary)
|
|
|
+ * where:
|
|
|
+ * f = Correction Report Filtering Bit. If 1, subsequent errors
|
|
|
+ * won't be shown
|
|
|
+ * mmm = error type
|
|
|
+ * cccc = channel
|
|
|
+ * If the mask doesn't match, report an error to the parsing logic
|
|
|
+ */
|
|
|
+ if (!((errcode & 0xef80) == 0x80)) {
|
|
|
+ optype = "Can't parse: it is not a mem";
|
|
|
+ } else {
|
|
|
+ switch (optypenum) {
|
|
|
+ case 0:
|
|
|
+ optype = "generic undef request error";
|
|
|
+ break;
|
|
|
+ case 1:
|
|
|
+ optype = "memory read error";
|
|
|
+ break;
|
|
|
+ case 2:
|
|
|
+ optype = "memory write error";
|
|
|
+ break;
|
|
|
+ case 3:
|
|
|
+ optype = "addr/cmd error";
|
|
|
+ break;
|
|
|
+ case 4:
|
|
|
+ optype = "memory scrubbing error";
|
|
|
+ break;
|
|
|
+ default:
|
|
|
+ optype = "reserved";
|
|
|
+ break;
|
|
|
+ }
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Only decode errors with an valid address (ADDRV) */
|
|
|
+ if (!(m->status & MCI_STATUS_ADDRV))
|
|
|
+ return;
|
|
|
+
|
|
|
+ rc = get_memory_error_data(mci, m->addr, daddr, msg);
|
|
|
+ if (rc)
|
|
|
+ goto address_error;
|
|
|
+
|
|
|
+ snprintf(msg, sizeof(msg),
|
|
|
+ "%s%s err_code:%04x:%04x channel:%d DIMM:%d rank:%d row:%d bank:%d col:%d",
|
|
|
+ overflow ? " OVERFLOW" : "", (uc_err && recov) ? " recoverable" : "", mscod,
|
|
|
+ errcode, daddr->chan, daddr->dimm, daddr->rank, daddr->row, daddr->bank, daddr->col);
|
|
|
+
|
|
|
+ edac_dbg(0, "%s\n", msg);
|
|
|
+
|
|
|
+ /* Call the helper to output message */
|
|
|
+ edac_mc_handle_error(tp_event, mci, core_err_cnt, m->addr >> PAGE_SHIFT,
|
|
|
+ m->addr & ~PAGE_MASK, 0, daddr->chan, daddr->dimm, -1, optype, msg);
|
|
|
+
|
|
|
+ return;
|
|
|
+
|
|
|
+address_error:
|
|
|
+ edac_mc_handle_error(tp_event, mci, core_err_cnt, 0, 0, 0, -1, -1, -1, msg, "");
|
|
|
+}
|
|
|
+
|
|
|
+static void apl_get_dimm_config(struct mem_ctl_info *mci)
|
|
|
+{
|
|
|
+ struct pnd2_pvt *pvt = mci->pvt_info;
|
|
|
+ struct dimm_info *dimm;
|
|
|
+ struct d_cr_drp0 *d;
|
|
|
+ u64 capacity;
|
|
|
+ int i, g;
|
|
|
+
|
|
|
+ for (i = 0; i < APL_NUM_CHANNELS; i++) {
|
|
|
+ if (!(chan_mask & BIT(i)))
|
|
|
+ continue;
|
|
|
+
|
|
|
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, 0, 0);
|
|
|
+ if (!dimm) {
|
|
|
+ edac_dbg(0, "No allocated DIMM for channel %d\n", i);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ d = &drp0[i];
|
|
|
+ for (g = 0; g < ARRAY_SIZE(dimms); g++)
|
|
|
+ if (dimms[g].addrdec == d->addrdec &&
|
|
|
+ dimms[g].dden == d->dden &&
|
|
|
+ dimms[g].dwid == d->dwid)
|
|
|
+ break;
|
|
|
+
|
|
|
+ if (g == ARRAY_SIZE(dimms)) {
|
|
|
+ edac_dbg(0, "Channel %d: unrecognized DIMM\n", i);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ pvt->dimm_geom[i] = g;
|
|
|
+ capacity = (d->rken0 + d->rken1) * 8 * (1ul << dimms[g].rowbits) *
|
|
|
+ (1ul << dimms[g].colbits);
|
|
|
+ edac_dbg(0, "Channel %d: %lld MByte DIMM\n", i, capacity >> (20 - 3));
|
|
|
+ dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));
|
|
|
+ dimm->grain = 32;
|
|
|
+ dimm->dtype = (d->dwid == 0) ? DEV_X8 : DEV_X16;
|
|
|
+ dimm->mtype = MEM_DDR3;
|
|
|
+ dimm->edac_mode = EDAC_SECDED;
|
|
|
+ snprintf(dimm->label, sizeof(dimm->label), "Slice#%d_Chan#%d", i / 2, i % 2);
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static const int dnv_dtypes[] = {
|
|
|
+ DEV_X8, DEV_X4, DEV_X16, DEV_UNKNOWN
|
|
|
+};
|
|
|
+
|
|
|
+static void dnv_get_dimm_config(struct mem_ctl_info *mci)
|
|
|
+{
|
|
|
+ int i, j, ranks_of_dimm[DNV_MAX_DIMMS], banks, rowbits, colbits, memtype;
|
|
|
+ struct dimm_info *dimm;
|
|
|
+ struct d_cr_drp *d;
|
|
|
+ u64 capacity;
|
|
|
+
|
|
|
+ if (dsch.ddr4en) {
|
|
|
+ memtype = MEM_DDR4;
|
|
|
+ banks = 16;
|
|
|
+ colbits = 10;
|
|
|
+ } else {
|
|
|
+ memtype = MEM_DDR3;
|
|
|
+ banks = 8;
|
|
|
+ }
|
|
|
+
|
|
|
+ for (i = 0; i < DNV_NUM_CHANNELS; i++) {
|
|
|
+ if (dmap4[i].row14 == 31)
|
|
|
+ rowbits = 14;
|
|
|
+ else if (dmap4[i].row15 == 31)
|
|
|
+ rowbits = 15;
|
|
|
+ else if (dmap4[i].row16 == 31)
|
|
|
+ rowbits = 16;
|
|
|
+ else if (dmap4[i].row17 == 31)
|
|
|
+ rowbits = 17;
|
|
|
+ else
|
|
|
+ rowbits = 18;
|
|
|
+
|
|
|
+ if (memtype == MEM_DDR3) {
|
|
|
+ if (dmap1[i].ca11 != 0x3f)
|
|
|
+ colbits = 12;
|
|
|
+ else
|
|
|
+ colbits = 10;
|
|
|
+ }
|
|
|
+
|
|
|
+ d = &drp[i];
|
|
|
+ /* DIMM0 is present if rank0 and/or rank1 is enabled */
|
|
|
+ ranks_of_dimm[0] = d->rken0 + d->rken1;
|
|
|
+ /* DIMM1 is present if rank2 and/or rank3 is enabled */
|
|
|
+ ranks_of_dimm[1] = d->rken2 + d->rken3;
|
|
|
+
|
|
|
+ for (j = 0; j < DNV_MAX_DIMMS; j++) {
|
|
|
+ if (!ranks_of_dimm[j])
|
|
|
+ continue;
|
|
|
+
|
|
|
+ dimm = EDAC_DIMM_PTR(mci->layers, mci->dimms, mci->n_layers, i, j, 0);
|
|
|
+ if (!dimm) {
|
|
|
+ edac_dbg(0, "No allocated DIMM for channel %d DIMM %d\n", i, j);
|
|
|
+ continue;
|
|
|
+ }
|
|
|
+
|
|
|
+ capacity = ranks_of_dimm[j] * banks * (1ul << rowbits) * (1ul << colbits);
|
|
|
+ edac_dbg(0, "Channel %d DIMM %d: %lld MByte DIMM\n", i, j, capacity >> (20 - 3));
|
|
|
+ dimm->nr_pages = MiB_TO_PAGES(capacity >> (20 - 3));
|
|
|
+ dimm->grain = 32;
|
|
|
+ dimm->dtype = dnv_dtypes[j ? d->dimmdwid0 : d->dimmdwid1];
|
|
|
+ dimm->mtype = memtype;
|
|
|
+ dimm->edac_mode = EDAC_SECDED;
|
|
|
+ snprintf(dimm->label, sizeof(dimm->label), "Chan#%d_DIMM#%d", i, j);
|
|
|
+ }
|
|
|
+ }
|
|
|
+}
|
|
|
+
|
|
|
+static int pnd2_register_mci(struct mem_ctl_info **ppmci)
|
|
|
+{
|
|
|
+ struct edac_mc_layer layers[2];
|
|
|
+ struct mem_ctl_info *mci;
|
|
|
+ struct pnd2_pvt *pvt;
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ rc = ops->check_ecc();
|
|
|
+ if (rc < 0)
|
|
|
+ return rc;
|
|
|
+
|
|
|
+ /* Allocate a new MC control structure */
|
|
|
+ layers[0].type = EDAC_MC_LAYER_CHANNEL;
|
|
|
+ layers[0].size = ops->channels;
|
|
|
+ layers[0].is_virt_csrow = false;
|
|
|
+ layers[1].type = EDAC_MC_LAYER_SLOT;
|
|
|
+ layers[1].size = ops->dimms_per_channel;
|
|
|
+ layers[1].is_virt_csrow = true;
|
|
|
+ mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
|
|
|
+ if (!mci)
|
|
|
+ return -ENOMEM;
|
|
|
+
|
|
|
+ pvt = mci->pvt_info;
|
|
|
+ memset(pvt, 0, sizeof(*pvt));
|
|
|
+
|
|
|
+ mci->mod_name = "pnd2_edac.c";
|
|
|
+ mci->dev_name = ops->name;
|
|
|
+ mci->ctl_name = "Pondicherry2";
|
|
|
+
|
|
|
+ /* Get dimm basic config and the memory layout */
|
|
|
+ ops->get_dimm_config(mci);
|
|
|
+
|
|
|
+ if (edac_mc_add_mc(mci)) {
|
|
|
+ edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
|
|
|
+ edac_mc_free(mci);
|
|
|
+ return -EINVAL;
|
|
|
+ }
|
|
|
+
|
|
|
+ *ppmci = mci;
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void pnd2_unregister_mci(struct mem_ctl_info *mci)
|
|
|
+{
|
|
|
+ if (unlikely(!mci || !mci->pvt_info)) {
|
|
|
+ pnd2_printk(KERN_ERR, "Couldn't find mci handler\n");
|
|
|
+ return;
|
|
|
+ }
|
|
|
+
|
|
|
+ /* Remove MC sysfs nodes */
|
|
|
+ edac_mc_del_mc(NULL);
|
|
|
+ edac_dbg(1, "%s: free mci struct\n", mci->ctl_name);
|
|
|
+ edac_mc_free(mci);
|
|
|
+}
|
|
|
+
|
|
|
+/*
|
|
|
+ * Callback function registered with core kernel mce code.
|
|
|
+ * Called once for each logged error.
|
|
|
+ */
|
|
|
+static int pnd2_mce_check_error(struct notifier_block *nb, unsigned long val, void *data)
|
|
|
+{
|
|
|
+ struct mce *mce = (struct mce *)data;
|
|
|
+ struct mem_ctl_info *mci;
|
|
|
+ struct dram_addr daddr;
|
|
|
+ char *type;
|
|
|
+
|
|
|
+ if (get_edac_report_status() == EDAC_REPORTING_DISABLED)
|
|
|
+ return NOTIFY_DONE;
|
|
|
+
|
|
|
+ mci = pnd2_mci;
|
|
|
+ if (!mci)
|
|
|
+ return NOTIFY_DONE;
|
|
|
+
|
|
|
+ /*
|
|
|
+ * Just let mcelog handle it if the error is
|
|
|
+ * outside the memory controller. A memory error
|
|
|
+ * is indicated by bit 7 = 1 and bits = 8-11,13-15 = 0.
|
|
|
+ * bit 12 has an special meaning.
|
|
|
+ */
|
|
|
+ if ((mce->status & 0xefff) >> 7 != 1)
|
|
|
+ return NOTIFY_DONE;
|
|
|
+
|
|
|
+ if (mce->mcgstatus & MCG_STATUS_MCIP)
|
|
|
+ type = "Exception";
|
|
|
+ else
|
|
|
+ type = "Event";
|
|
|
+
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "HANDLING MCE MEMORY ERROR\n");
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "CPU %u: Machine Check %s: %llx Bank %u: %llx\n",
|
|
|
+ mce->extcpu, type, mce->mcgstatus, mce->bank, mce->status);
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "TSC %llx ", mce->tsc);
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "ADDR %llx ", mce->addr);
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "MISC %llx ", mce->misc);
|
|
|
+ pnd2_mc_printk(mci, KERN_INFO, "PROCESSOR %u:%x TIME %llu SOCKET %u APIC %x\n",
|
|
|
+ mce->cpuvendor, mce->cpuid, mce->time, mce->socketid, mce->apicid);
|
|
|
+
|
|
|
+ pnd2_mce_output_error(mci, mce, &daddr);
|
|
|
+
|
|
|
+ /* Advice mcelog that the error were handled */
|
|
|
+ return NOTIFY_STOP;
|
|
|
+}
|
|
|
+
|
|
|
+static struct notifier_block pnd2_mce_dec = {
|
|
|
+ .notifier_call = pnd2_mce_check_error,
|
|
|
+};
|
|
|
+
|
|
|
+#ifdef CONFIG_EDAC_DEBUG
|
|
|
+/*
|
|
|
+ * Write an address to this file to exercise the address decode
|
|
|
+ * logic in this driver.
|
|
|
+ */
|
|
|
+static u64 pnd2_fake_addr;
|
|
|
+#define PND2_BLOB_SIZE 1024
|
|
|
+static char pnd2_result[PND2_BLOB_SIZE];
|
|
|
+static struct dentry *pnd2_test;
|
|
|
+static struct debugfs_blob_wrapper pnd2_blob = {
|
|
|
+ .data = pnd2_result,
|
|
|
+ .size = 0
|
|
|
+};
|
|
|
+
|
|
|
+static int debugfs_u64_set(void *data, u64 val)
|
|
|
+{
|
|
|
+ struct dram_addr daddr;
|
|
|
+ struct mce m;
|
|
|
+
|
|
|
+ *(u64 *)data = val;
|
|
|
+ m.mcgstatus = 0;
|
|
|
+ /* ADDRV + MemRd + Unknown channel */
|
|
|
+ m.status = MCI_STATUS_ADDRV + 0x9f;
|
|
|
+ m.addr = val;
|
|
|
+ pnd2_mce_output_error(pnd2_mci, &m, &daddr);
|
|
|
+ snprintf(pnd2_blob.data, PND2_BLOB_SIZE,
|
|
|
+ "SysAddr=%llx Channel=%d DIMM=%d Rank=%d Bank=%d Row=%d Column=%d\n",
|
|
|
+ m.addr, daddr.chan, daddr.dimm, daddr.rank, daddr.bank, daddr.row, daddr.col);
|
|
|
+ pnd2_blob.size = strlen(pnd2_blob.data);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+DEFINE_DEBUGFS_ATTRIBUTE(fops_u64_wo, NULL, debugfs_u64_set, "%llu\n");
|
|
|
+
|
|
|
+static void setup_pnd2_debug(void)
|
|
|
+{
|
|
|
+ pnd2_test = edac_debugfs_create_dir("pnd2_test");
|
|
|
+ edac_debugfs_create_file("pnd2_debug_addr", 0200, pnd2_test,
|
|
|
+ &pnd2_fake_addr, &fops_u64_wo);
|
|
|
+ debugfs_create_blob("pnd2_debug_results", 0400, pnd2_test, &pnd2_blob);
|
|
|
+}
|
|
|
+
|
|
|
+static void teardown_pnd2_debug(void)
|
|
|
+{
|
|
|
+ debugfs_remove_recursive(pnd2_test);
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|
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+}
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|
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+#else
|
|
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+static void setup_pnd2_debug(void) {}
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|
|
+static void teardown_pnd2_debug(void) {}
|
|
|
+#endif /* CONFIG_EDAC_DEBUG */
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|
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+
|
|
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+
|
|
|
+static int pnd2_probe(void)
|
|
|
+{
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|
|
+ int rc;
|
|
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+
|
|
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+ edac_dbg(2, "\n");
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|
|
+ rc = get_registers();
|
|
|
+ if (rc)
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|
|
+ return rc;
|
|
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+
|
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+ return pnd2_register_mci(&pnd2_mci);
|
|
|
+}
|
|
|
+
|
|
|
+static void pnd2_remove(void)
|
|
|
+{
|
|
|
+ edac_dbg(0, "\n");
|
|
|
+ pnd2_unregister_mci(pnd2_mci);
|
|
|
+}
|
|
|
+
|
|
|
+static struct dunit_ops apl_ops = {
|
|
|
+ .name = "pnd2/apl",
|
|
|
+ .type = APL,
|
|
|
+ .pmiaddr_shift = LOG2_PMI_ADDR_GRANULARITY,
|
|
|
+ .pmiidx_shift = 0,
|
|
|
+ .channels = APL_NUM_CHANNELS,
|
|
|
+ .dimms_per_channel = 1,
|
|
|
+ .rd_reg = apl_rd_reg,
|
|
|
+ .get_registers = apl_get_registers,
|
|
|
+ .check_ecc = apl_check_ecc_active,
|
|
|
+ .mk_region = apl_mk_region,
|
|
|
+ .get_dimm_config = apl_get_dimm_config,
|
|
|
+ .pmi2mem = apl_pmi2mem,
|
|
|
+};
|
|
|
+
|
|
|
+static struct dunit_ops dnv_ops = {
|
|
|
+ .name = "pnd2/dnv",
|
|
|
+ .type = DNV,
|
|
|
+ .pmiaddr_shift = 0,
|
|
|
+ .pmiidx_shift = 1,
|
|
|
+ .channels = DNV_NUM_CHANNELS,
|
|
|
+ .dimms_per_channel = 2,
|
|
|
+ .rd_reg = dnv_rd_reg,
|
|
|
+ .get_registers = dnv_get_registers,
|
|
|
+ .check_ecc = dnv_check_ecc_active,
|
|
|
+ .mk_region = dnv_mk_region,
|
|
|
+ .get_dimm_config = dnv_get_dimm_config,
|
|
|
+ .pmi2mem = dnv_pmi2mem,
|
|
|
+};
|
|
|
+
|
|
|
+static const struct x86_cpu_id pnd2_cpuids[] = {
|
|
|
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_GOLDMONT, 0, (kernel_ulong_t)&apl_ops },
|
|
|
+ { X86_VENDOR_INTEL, 6, INTEL_FAM6_ATOM_DENVERTON, 0, (kernel_ulong_t)&dnv_ops },
|
|
|
+ { }
|
|
|
+};
|
|
|
+MODULE_DEVICE_TABLE(x86cpu, pnd2_cpuids);
|
|
|
+
|
|
|
+static int __init pnd2_init(void)
|
|
|
+{
|
|
|
+ const struct x86_cpu_id *id;
|
|
|
+ int rc;
|
|
|
+
|
|
|
+ edac_dbg(2, "\n");
|
|
|
+
|
|
|
+ id = x86_match_cpu(pnd2_cpuids);
|
|
|
+ if (!id)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ ops = (struct dunit_ops *)id->driver_data;
|
|
|
+
|
|
|
+ /* Ensure that the OPSTATE is set correctly for POLL or NMI */
|
|
|
+ opstate_init();
|
|
|
+
|
|
|
+ rc = pnd2_probe();
|
|
|
+ if (rc < 0) {
|
|
|
+ pnd2_printk(KERN_ERR, "Failed to register device with error %d.\n", rc);
|
|
|
+ return rc;
|
|
|
+ }
|
|
|
+
|
|
|
+ if (!pnd2_mci)
|
|
|
+ return -ENODEV;
|
|
|
+
|
|
|
+ mce_register_decode_chain(&pnd2_mce_dec);
|
|
|
+ setup_pnd2_debug();
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+
|
|
|
+static void __exit pnd2_exit(void)
|
|
|
+{
|
|
|
+ edac_dbg(2, "\n");
|
|
|
+ teardown_pnd2_debug();
|
|
|
+ mce_unregister_decode_chain(&pnd2_mce_dec);
|
|
|
+ pnd2_remove();
|
|
|
+}
|
|
|
+
|
|
|
+module_init(pnd2_init);
|
|
|
+module_exit(pnd2_exit);
|
|
|
+
|
|
|
+module_param(edac_op_state, int, 0444);
|
|
|
+MODULE_PARM_DESC(edac_op_state, "EDAC Error Reporting state: 0=Poll,1=NMI");
|
|
|
+
|
|
|
+MODULE_LICENSE("GPL v2");
|
|
|
+MODULE_AUTHOR("Tony Luck");
|
|
|
+MODULE_DESCRIPTION("MC Driver for Intel SoC using Pondicherry memory controller");
|
Jens Axboe