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@@ -807,11 +807,6 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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{
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u32 val;
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- /* get iATU unroll support */
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- pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
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- dev_dbg(pp->dev, "iATU unroll: %s\n",
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- pp->iatu_unroll_enabled ? "enabled" : "disabled");
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-
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/* set the number of lanes */
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val = dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL);
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val &= ~PORT_LINK_MODE_MASK;
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@@ -882,6 +877,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
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* we should not program the ATU here.
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*/
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if (!pp->ops->rd_other_conf) {
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+ /* get iATU unroll support */
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+ pp->iatu_unroll_enabled = dw_pcie_iatu_unroll_enabled(pp);
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+ dev_dbg(pp->dev, "iATU unroll: %s\n",
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+ pp->iatu_unroll_enabled ? "enabled" : "disabled");
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+
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dw_pcie_prog_outbound_atu(pp, PCIE_ATU_REGION_INDEX0,
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PCIE_ATU_TYPE_MEM, pp->mem_base,
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pp->mem_bus_addr, pp->mem_size);
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