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@@ -33,6 +33,7 @@ struct ci_hdrc_platform_data {
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#define CI_HDRC_FORCE_FULLSPEED BIT(6)
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#define CI_HDRC_FORCE_FULLSPEED BIT(6)
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#define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7)
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#define CI_HDRC_TURN_VBUS_EARLY_ON BIT(7)
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#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8)
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#define CI_HDRC_SET_NON_ZERO_TTHA BIT(8)
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+#define CI_HDRC_OVERRIDE_AHB_BURST BIT(9)
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enum usb_dr_mode dr_mode;
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enum usb_dr_mode dr_mode;
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_RESET_EVENT 0
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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#define CI_HDRC_CONTROLLER_STOPPED_EVENT 1
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@@ -41,6 +42,7 @@ struct ci_hdrc_platform_data {
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bool tpl_support;
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bool tpl_support;
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/* interrupt threshold setting */
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/* interrupt threshold setting */
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u32 itc_setting;
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u32 itc_setting;
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+ u32 ahb_burst_config;
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};
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};
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/* Default offset of capability registers */
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/* Default offset of capability registers */
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