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@@ -29,6 +29,15 @@
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/******************************************************************************
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* REGISTERS
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*****************************************************************************/
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+/* Identification Registers */
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+#define ID_ID 0x0
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+#define ID_HWGENERAL 0x4
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+#define ID_HWHOST 0x8
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+#define ID_HWDEVICE 0xc
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+#define ID_HWTXBUF 0x10
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+#define ID_HWRXBUF 0x14
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+#define ID_SBUSCFG 0x90
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+
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/* register indices */
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enum ci_hw_regs {
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CAP_CAPLENGTH,
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@@ -253,6 +262,36 @@ static inline void ci_role_stop(struct ci_hdrc *ci)
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ci->roles[role]->stop(ci);
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}
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+/**
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+ * hw_read_id_reg: reads from a identification register
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+ * @ci: the controller
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+ * @offset: offset from the beginning of identification registers region
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+ * @mask: bitfield mask
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+ *
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+ * This function returns register contents
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+ */
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+static inline u32 hw_read_id_reg(struct ci_hdrc *ci, u32 offset, u32 mask)
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+{
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+ return ioread32(ci->hw_bank.abs + offset) & mask;
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+}
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+
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+/**
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+ * hw_write_id_reg: writes to a identification register
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+ * @ci: the controller
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+ * @offset: offset from the beginning of identification registers region
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+ * @mask: bitfield mask
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+ * @data: new value
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+ */
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+static inline void hw_write_id_reg(struct ci_hdrc *ci, u32 offset,
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+ u32 mask, u32 data)
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+{
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+ if (~mask)
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+ data = (ioread32(ci->hw_bank.abs + offset) & ~mask)
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+ | (data & mask);
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+
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+ iowrite32(data, ci->hw_bank.abs + offset);
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+}
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+
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/**
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* hw_read: reads from a hw register
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* @ci: the controller
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