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@@ -314,8 +314,9 @@ static void wil_target_reset(struct wil6210_priv *wil)
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int delay = 0;
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u32 hw_state;
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u32 rev_id;
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+ bool is_sparrow = (wil->board->board == WIL_BOARD_SPARROW);
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- wil_dbg_misc(wil, "Resetting...\n");
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+ wil_dbg_misc(wil, "Resetting \"%s\"...\n", wil->board->name);
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/* register read */
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#define R(a) ioread32(wil->csr + HOSTADDR(a))
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@@ -328,35 +329,59 @@ static void wil_target_reset(struct wil6210_priv *wil)
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wil->hw_version = R(RGF_USER_FW_REV_ID);
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rev_id = wil->hw_version & 0xff;
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+
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+ /* Clear MAC link up */
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+ S(RGF_HP_CTRL, BIT(15));
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/* hpal_perst_from_pad_src_n_mask */
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(6));
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/* car_perst_rst_src_n_mask */
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S(RGF_USER_CLKS_CTL_SW_RST_MASK_0, BIT(7));
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wmb(); /* order is important here */
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+ if (is_sparrow) {
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+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x3ff81f);
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+ wmb(); /* order is important here */
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+ }
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+
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W(RGF_USER_MAC_CPU_0, BIT(1)); /* mac_cpu_man_rst */
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W(RGF_USER_USER_CPU_0, BIT(1)); /* user_cpu_man_rst */
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wmb(); /* order is important here */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0xFE000000);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0x0000003F);
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- W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000170);
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+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, is_sparrow ? 0x000000B0 : 0x00000170);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0xFFE7FC00);
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wmb(); /* order is important here */
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+ if (is_sparrow) {
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+ W(RGF_USER_CLKS_CTL_EXT_SW_RST_VEC_0, 0x0);
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+ wmb(); /* order is important here */
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+ }
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+
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_1, 0);
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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wmb(); /* order is important here */
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- W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
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- if (rev_id == 1) {
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- W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
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- } else {
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- W(RGF_PCIE_LOS_COUNTER_CTL, BIT(6) | BIT(8));
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+ if (is_sparrow) {
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+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000003);
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+ /* reset A2 PCIE AHB */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
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+
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+ } else {
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+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_3, 0x00000001);
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+ if (rev_id == 1) {
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+ /* reset A1 BOTH PCIE AHB & PCIE RGF */
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+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00000080);
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+ } else {
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+ W(RGF_PCIE_LOS_COUNTER_CTL, BIT(6) | BIT(8));
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+ W(RGF_USER_CLKS_CTL_SW_RST_VEC_2, 0x00008000);
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+ }
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+
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}
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+
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+ /* TODO: check order here!!! Erez code is different */
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W(RGF_USER_CLKS_CTL_SW_RST_VEC_0, 0);
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wmb(); /* order is important here */
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@@ -371,7 +396,8 @@ static void wil_target_reset(struct wil6210_priv *wil)
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}
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} while (hw_state != HW_MACHINE_BOOT_DONE);
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- if (rev_id == 2)
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+ /* TODO: Erez check rev_id != 1 */
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+ if (!is_sparrow && (rev_id != 1))
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W(RGF_PCIE_LOS_COUNTER_CTL, BIT(8));
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C(RGF_USER_CLKS_CTL_0, BIT_USER_CLKS_RST_PWGD);
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