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@@ -518,7 +518,7 @@ enum clk_type_t {
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CLK_INT_SING = 2, /* Internal single ended */
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};
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-enum phy_mode {
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+enum xgene_phy_mode {
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MODE_SATA = 0, /* List them for simple reference */
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MODE_SGMII = 1,
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MODE_PCIE = 2,
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@@ -542,7 +542,7 @@ struct xgene_sata_override_param {
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struct xgene_phy_ctx {
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struct device *dev;
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struct phy *phy;
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- enum phy_mode mode; /* Mode of operation */
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+ enum xgene_phy_mode mode; /* Mode of operation */
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enum clk_type_t clk_type; /* Input clock selection */
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void __iomem *sds_base; /* PHY CSR base addr */
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struct clk *clk; /* Optional clock */
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