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@@ -101,9 +101,26 @@ enum {
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#define POWER9_MMCRA_IFM2 0x0000000080000000UL
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#define POWER9_MMCRA_IFM3 0x00000000C0000000UL
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+/* Nasty Power9 specific hack */
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+#define PVR_POWER9_CUMULUS 0x00002000
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+
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/* PowerISA v2.07 format attribute structure*/
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extern struct attribute_group isa207_pmu_format_group;
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+int p9_dd21_bl_ev[] = {
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+ PM_MRK_ST_DONE_L2,
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+ PM_RADIX_PWC_L1_HIT,
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+ PM_FLOP_CMPL,
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+ PM_MRK_NTF_FIN,
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+ PM_RADIX_PWC_L2_HIT,
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+ PM_IFETCH_THROTTLE,
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+ PM_MRK_L2_TM_ST_ABORT_SISTER,
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+ PM_RADIX_PWC_L3_HIT,
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+ PM_RUN_CYC_SMT2_MODE,
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+ PM_TM_TX_PASS_RUN_INST,
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+ PM_DISP_HELD_SYNC_HOLD,
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+};
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+
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/* Table of alternatives, sorted by column 0 */
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static const unsigned int power9_event_alternatives[][MAX_ALT] = {
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{ PM_INST_DISP, PM_INST_DISP_ALT },
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@@ -446,12 +463,21 @@ static struct power_pmu power9_pmu = {
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static int __init init_power9_pmu(void)
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{
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int rc = 0;
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+ unsigned int pvr = mfspr(SPRN_PVR);
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/* Comes from cpu_specs[] */
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if (!cur_cpu_spec->oprofile_cpu_type ||
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strcmp(cur_cpu_spec->oprofile_cpu_type, "ppc64/power9"))
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return -ENODEV;
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+ /* Blacklist events */
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+ if (!(pvr & PVR_POWER9_CUMULUS)) {
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+ if ((PVR_CFG(pvr) == 2) && (PVR_MIN(pvr) == 1)) {
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+ power9_pmu.blacklist_ev = p9_dd21_bl_ev;
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+ power9_pmu.n_blacklist_ev = ARRAY_SIZE(p9_dd21_bl_ev);
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+ }
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+ }
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+
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if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
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/*
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* Since PM_INST_CMPL may not provide right counts in all
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