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@@ -46,6 +46,7 @@
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#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
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#define CTOP_AUX_UDMC (CTOP_AUX_BASE + 0x300)
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/* EZchip core instructions */
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/* EZchip core instructions */
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+#define CTOP_INST_HWSCHD_WFT_IE12 0x3E6F7344
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#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
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#define CTOP_INST_HWSCHD_OFF_R4 0x3C6F00BF
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#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
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#define CTOP_INST_HWSCHD_RESTORE_R4 0x3E6F7103
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#define CTOP_INST_SCHD_RW 0x3E6F7004
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#define CTOP_INST_SCHD_RW 0x3E6F7004
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