|
@@ -77,6 +77,7 @@ struct dwapb_context {
|
|
|
u32 int_type;
|
|
|
u32 int_pol;
|
|
|
u32 int_deb;
|
|
|
+ u32 wake_en;
|
|
|
};
|
|
|
#endif
|
|
|
|
|
@@ -295,6 +296,22 @@ static int dwapb_irq_set_type(struct irq_data *d, u32 type)
|
|
|
return 0;
|
|
|
}
|
|
|
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+static int dwapb_irq_set_wake(struct irq_data *d, unsigned int enable)
|
|
|
+{
|
|
|
+ struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
|
|
|
+ struct dwapb_gpio *gpio = igc->private;
|
|
|
+ struct dwapb_context *ctx = gpio->ports[0].ctx;
|
|
|
+
|
|
|
+ if (enable)
|
|
|
+ ctx->wake_en |= BIT(d->hwirq);
|
|
|
+ else
|
|
|
+ ctx->wake_en &= ~BIT(d->hwirq);
|
|
|
+
|
|
|
+ return 0;
|
|
|
+}
|
|
|
+#endif
|
|
|
+
|
|
|
static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
|
|
|
unsigned offset, unsigned debounce)
|
|
|
{
|
|
@@ -385,6 +402,9 @@ static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
|
|
|
ct->chip.irq_disable = dwapb_irq_disable;
|
|
|
ct->chip.irq_request_resources = dwapb_irq_reqres;
|
|
|
ct->chip.irq_release_resources = dwapb_irq_relres;
|
|
|
+#ifdef CONFIG_PM_SLEEP
|
|
|
+ ct->chip.irq_set_wake = dwapb_irq_set_wake;
|
|
|
+#endif
|
|
|
ct->regs.ack = gpio_reg_convert(gpio, GPIO_PORTA_EOI);
|
|
|
ct->regs.mask = gpio_reg_convert(gpio, GPIO_INTMASK);
|
|
|
ct->type = IRQ_TYPE_LEVEL_MASK;
|
|
@@ -699,7 +719,8 @@ static int dwapb_gpio_suspend(struct device *dev)
|
|
|
ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
|
|
|
|
|
|
/* Mask out interrupts */
|
|
|
- dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
|
|
|
+ dwapb_write(gpio, GPIO_INTMASK,
|
|
|
+ 0xffffffff & ~ctx->wake_en);
|
|
|
}
|
|
|
}
|
|
|
spin_unlock_irqrestore(&gc->bgpio_lock, flags);
|