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@@ -70,6 +70,19 @@ enum PP_Result {
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#define PCIE_PERF_REQ_GEN2 3
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#define PCIE_PERF_REQ_GEN3 4
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+enum PP_FEATURE_MASK {
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+ PP_SCLK_DPM_MASK = 0x1,
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+ PP_MCLK_DPM_MASK = 0x2,
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+ PP_PCIE_DPM_MASK = 0x4,
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+ PP_SCLK_DEEP_SLEEP_MASK = 0x8,
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+ PP_POWER_CONTAINMENT_MASK = 0x10,
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+ PP_UVD_HANDSHAKE_MASK = 0x20,
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+ PP_SMC_VOLTAGE_CONTROL_MASK = 0x40,
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+ PP_VBI_TIME_SUPPORT_MASK = 0x80,
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+ PP_ULV_MASK = 0x100,
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+ PP_ENABLE_GFX_CG_THRU_SMU = 0x200
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+};
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+
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enum PHM_BackEnd_Magic {
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PHM_Dummy_Magic = 0xAA5555AA,
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PHM_RV770_Magic = 0xDCBAABCD,
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@@ -635,6 +648,7 @@ struct pp_hwmgr {
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struct pp_power_state *boot_ps;
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struct pp_power_state *uvd_ps;
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struct amd_pp_display_configuration display_config;
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+ uint32_t feature_mask;
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};
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