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@@ -30,7 +30,6 @@ extern void secondary_holding_pen(void);
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volatile unsigned long secondary_holding_pen_release = INVALID_HWID;
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static phys_addr_t cpu_release_addr[NR_CPUS];
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-static DEFINE_RAW_SPINLOCK(boot_lock);
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/*
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* Write secondary_holding_pen_release in a way that is guaranteed to be
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@@ -94,14 +93,6 @@ static int smp_spin_table_cpu_prepare(unsigned int cpu)
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static int smp_spin_table_cpu_boot(unsigned int cpu)
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{
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- unsigned long timeout;
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-
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- /*
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- * Set synchronisation state between this boot processor
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- * and the secondary one
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- */
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- raw_spin_lock(&boot_lock);
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-
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/*
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* Update the pen release flag.
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*/
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@@ -112,34 +103,7 @@ static int smp_spin_table_cpu_boot(unsigned int cpu)
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*/
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sev();
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- timeout = jiffies + (1 * HZ);
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- while (time_before(jiffies, timeout)) {
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- if (secondary_holding_pen_release == INVALID_HWID)
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- break;
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- udelay(10);
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- }
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-
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- /*
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- * Now the secondary core is starting up let it run its
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- * calibrations, then wait for it to finish
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- */
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- raw_spin_unlock(&boot_lock);
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-
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- return secondary_holding_pen_release != INVALID_HWID ? -ENOSYS : 0;
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-}
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-
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-static void smp_spin_table_cpu_postboot(void)
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-{
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- /*
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- * Let the primary processor know we're out of the pen.
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- */
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- write_pen_release(INVALID_HWID);
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-
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- /*
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- * Synchronise with the boot thread.
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- */
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- raw_spin_lock(&boot_lock);
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- raw_spin_unlock(&boot_lock);
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+ return 0;
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}
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const struct cpu_operations smp_spin_table_ops = {
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@@ -147,5 +111,4 @@ const struct cpu_operations smp_spin_table_ops = {
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.cpu_init = smp_spin_table_cpu_init,
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.cpu_prepare = smp_spin_table_cpu_prepare,
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.cpu_boot = smp_spin_table_cpu_boot,
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- .cpu_postboot = smp_spin_table_cpu_postboot,
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};
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