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@@ -1937,6 +1937,24 @@ int amdgpu_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
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return 0;
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}
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+static bool amdgpu_check_soft_reset(struct amdgpu_device *adev)
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+{
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+ int i;
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+ bool asic_hang = false;
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+
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+ for (i = 0; i < adev->num_ip_blocks; i++) {
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+ if (!adev->ip_block_status[i].valid)
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+ continue;
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+ if (adev->ip_blocks[i].funcs->check_soft_reset)
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+ adev->ip_blocks[i].funcs->check_soft_reset(adev);
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+ if (adev->ip_block_status[i].hang) {
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+ DRM_INFO("IP block:%d is hang!\n", i);
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+ asic_hang = true;
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+ }
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+ }
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+ return asic_hang;
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+}
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+
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/**
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* amdgpu_gpu_reset - reset the asic
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*
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@@ -1950,6 +1968,11 @@ int amdgpu_gpu_reset(struct amdgpu_device *adev)
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int i, r;
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int resched;
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+ if (!amdgpu_check_soft_reset(adev)) {
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+ DRM_INFO("No hardware hang detected. Did some blocks stall?\n");
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+ return 0;
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+ }
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+
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atomic_inc(&adev->gpu_reset_counter);
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/* block TTM */
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