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@@ -309,6 +309,13 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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ib_size_alignment = 1;
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break;
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+ case AMDGPU_HW_IP_UVD_ENC:
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+ type = AMD_IP_BLOCK_TYPE_UVD;
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+ for (i = 0; i < adev->uvd.num_enc_rings; i++)
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+ ring_mask |= ((adev->uvd.ring_enc[i].ready ? 1 : 0) << i);
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+ ib_start_alignment = AMDGPU_GPU_PAGE_SIZE;
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+ ib_size_alignment = 1;
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+ break;
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default:
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return -EINVAL;
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}
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@@ -348,6 +355,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
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case AMDGPU_HW_IP_VCE:
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type = AMD_IP_BLOCK_TYPE_VCE;
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break;
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+ case AMDGPU_HW_IP_UVD_ENC:
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+ type = AMD_IP_BLOCK_TYPE_UVD;
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+ break;
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default:
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return -EINVAL;
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}
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