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@@ -2391,6 +2391,27 @@ done:
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uart_update_timeout(port, termios->c_cflag, baud);
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+ /* byte size and parity */
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+ switch (termios->c_cflag & CSIZE) {
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+ case CS5:
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+ bits = 7;
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+ break;
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+ case CS6:
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+ bits = 8;
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+ break;
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+ case CS7:
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+ bits = 9;
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+ break;
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+ default:
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+ bits = 10;
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+ break;
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+ }
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+
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+ if (termios->c_cflag & CSTOPB)
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+ bits++;
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+ if (termios->c_cflag & PARENB)
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+ bits++;
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+
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if (best_clk >= 0) {
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if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
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switch (srr + 1) {
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@@ -2407,8 +2428,27 @@ done:
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serial_port_out(port, SCSCR, scr_val | s->hscif_tot);
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serial_port_out(port, SCSMR, smr_val);
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serial_port_out(port, SCBRR, brr);
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- if (sci_getreg(port, HSSRR)->size)
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- serial_port_out(port, HSSRR, srr | HSCIF_SRE);
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+ if (sci_getreg(port, HSSRR)->size) {
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+ unsigned int hssrr = srr | HSCIF_SRE;
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+ /* Calculate deviation from intended rate at the
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+ * center of the last stop bit in sampling clocks.
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+ */
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+ int last_stop = bits * 2 - 1;
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+ int deviation = min_err * srr * last_stop / 2 / baud;
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+
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+ if (abs(deviation) >= 2) {
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+ /* At least two sampling clocks off at the
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+ * last stop bit; we can increase the error
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+ * margin by shifting the sampling point.
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+ */
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+ int shift = min(-8, max(7, deviation / 2));
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+
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+ hssrr |= (shift << HSCIF_SRHP_SHIFT) &
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+ HSCIF_SRHP_MASK;
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+ hssrr |= HSCIF_SRDE;
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+ }
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+ serial_port_out(port, HSSRR, hssrr);
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+ }
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/* Wait one bit interval */
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udelay((1000000 + (baud - 1)) / baud);
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@@ -2475,27 +2515,6 @@ done:
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* value obtained by this formula is too small. Therefore, if the value
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* is smaller than 20ms, use 20ms as the timeout value for DMA.
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*/
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- /* byte size and parity */
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- switch (termios->c_cflag & CSIZE) {
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- case CS5:
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- bits = 7;
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- break;
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- case CS6:
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- bits = 8;
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- break;
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- case CS7:
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- bits = 9;
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- break;
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- default:
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- bits = 10;
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- break;
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- }
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-
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- if (termios->c_cflag & CSTOPB)
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- bits++;
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- if (termios->c_cflag & PARENB)
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- bits++;
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-
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s->rx_frame = (10000 * bits) / (baud / 100);
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#ifdef CONFIG_SERIAL_SH_SCI_DMA
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s->rx_timeout = s->buf_len_rx * 2 * s->rx_frame;
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