|
@@ -1368,7 +1368,17 @@ struct amdgpu_nbio_funcs {
|
|
void (*detect_hw_virt)(struct amdgpu_device *adev);
|
|
void (*detect_hw_virt)(struct amdgpu_device *adev);
|
|
};
|
|
};
|
|
|
|
|
|
-
|
|
|
|
|
|
+struct amdgpu_df_funcs {
|
|
|
|
+ void (*init)(struct amdgpu_device *adev);
|
|
|
|
+ void (*enable_broadcast_mode)(struct amdgpu_device *adev,
|
|
|
|
+ bool enable);
|
|
|
|
+ u32 (*get_fb_channel_number)(struct amdgpu_device *adev);
|
|
|
|
+ u32 (*get_hbm_channel_number)(struct amdgpu_device *adev);
|
|
|
|
+ void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev,
|
|
|
|
+ bool enable);
|
|
|
|
+ void (*get_clockgating_state)(struct amdgpu_device *adev,
|
|
|
|
+ u32 *flags);
|
|
|
|
+};
|
|
/* Define the HW IP blocks will be used in driver , add more if necessary */
|
|
/* Define the HW IP blocks will be used in driver , add more if necessary */
|
|
enum amd_hw_ip_block_type {
|
|
enum amd_hw_ip_block_type {
|
|
GC_HWIP = 1,
|
|
GC_HWIP = 1,
|
|
@@ -1588,6 +1598,7 @@ struct amdgpu_device {
|
|
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
|
uint32_t *reg_offset[MAX_HWIP][HWIP_MAX_INSTANCE];
|
|
|
|
|
|
const struct amdgpu_nbio_funcs *nbio_funcs;
|
|
const struct amdgpu_nbio_funcs *nbio_funcs;
|
|
|
|
+ const struct amdgpu_df_funcs *df_funcs;
|
|
|
|
|
|
/* delayed work_func for deferring clockgating during resume */
|
|
/* delayed work_func for deferring clockgating during resume */
|
|
struct delayed_work late_init_work;
|
|
struct delayed_work late_init_work;
|