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@@ -692,7 +692,8 @@ static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host,
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static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
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struct mmc_ios *ios)
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{
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- u32 rate, rval, clock = ios->clock;
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+ long rate;
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+ u32 rval, clock = ios->clock;
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int ret;
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/* 8 bit DDR requires a higher module clock */
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@@ -701,13 +702,18 @@ static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host,
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clock <<= 1;
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rate = clk_round_rate(host->clk_mmc, clock);
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- dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n",
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+ if (rate < 0) {
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+ dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n",
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+ clock, rate);
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+ return rate;
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+ }
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+ dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n",
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clock, rate);
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/* setting clock rate */
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ret = clk_set_rate(host->clk_mmc, rate);
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if (ret) {
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- dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n",
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+ dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n",
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rate, ret);
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return ret;
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}
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