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@@ -7677,10 +7677,8 @@ void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
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}
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/* Set up chip specific power management-related functions */
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-void intel_init_pm(struct drm_device *dev)
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+void intel_init_pm(struct drm_i915_private *dev_priv)
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{
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- struct drm_i915_private *dev_priv = to_i915(dev);
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-
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intel_fbc_init(dev_priv);
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/* For cxsr */
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@@ -7690,7 +7688,7 @@ void intel_init_pm(struct drm_device *dev)
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i915_ironlake_get_mem_freq(dev_priv);
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/* For FIFO watermark updates */
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- if (INTEL_INFO(dev)->gen >= 9) {
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+ if (INTEL_GEN(dev_priv) >= 9) {
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skl_setup_wm_latency(dev_priv);
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dev_priv->display.update_wm = skl_update_wm;
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dev_priv->display.compute_global_watermarks = skl_compute_wm;
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@@ -7741,7 +7739,7 @@ void intel_init_pm(struct drm_device *dev)
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dev_priv->display.update_wm = i9xx_update_wm;
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dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
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} else if (IS_GEN2(dev_priv)) {
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- if (INTEL_INFO(dev)->num_pipes == 1) {
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+ if (INTEL_INFO(dev_priv)->num_pipes == 1) {
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dev_priv->display.update_wm = i845_update_wm;
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dev_priv->display.get_fifo_size = i845_get_fifo_size;
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} else {
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