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@@ -189,7 +189,7 @@ static void xgene_pllclk_init(struct device_node *np, enum xgene_pll_type pll_ty
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int version = xgene_pllclk_version(np);
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reg = of_iomap(np, 0);
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- if (reg == NULL) {
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+ if (!reg) {
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pr_err("Unable to map CSR register for %pOF\n", np);
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return;
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}
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@@ -465,7 +465,7 @@ static int xgene_clk_enable(struct clk_hw *hw)
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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- if (pclk->param.csr_reg != NULL) {
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+ if (pclk->param.csr_reg) {
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pr_debug("%s clock enabled\n", clk_hw_get_name(hw));
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/* First enable the clock */
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data = xgene_clk_read(pclk->param.csr_reg +
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@@ -505,7 +505,7 @@ static void xgene_clk_disable(struct clk_hw *hw)
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if (pclk->lock)
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spin_lock_irqsave(pclk->lock, flags);
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- if (pclk->param.csr_reg != NULL) {
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+ if (pclk->param.csr_reg) {
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pr_debug("%s clock disabled\n", clk_hw_get_name(hw));
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/* First put the CSR in reset */
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data = xgene_clk_read(pclk->param.csr_reg +
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@@ -531,7 +531,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
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struct xgene_clk *pclk = to_xgene_clk(hw);
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u32 data = 0;
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- if (pclk->param.csr_reg != NULL) {
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+ if (pclk->param.csr_reg) {
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pr_debug("%s clock checking\n", clk_hw_get_name(hw));
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data = xgene_clk_read(pclk->param.csr_reg +
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pclk->param.reg_clk_offset);
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@@ -540,7 +540,7 @@ static int xgene_clk_is_enabled(struct clk_hw *hw)
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"disabled");
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}
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- if (pclk->param.csr_reg == NULL)
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+ if (!pclk->param.csr_reg)
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return 1;
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return data & pclk->param.reg_clk_mask ? 1 : 0;
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}
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@@ -705,7 +705,7 @@ static void __init xgene_devclk_init(struct device_node *np)
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break;
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}
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map_res = of_iomap(np, i);
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- if (map_res == NULL) {
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+ if (!map_res) {
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pr_err("Unable to map resource %d for %pOF\n", i, np);
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goto err;
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}
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