|
@@ -253,7 +253,8 @@ static void vcn_v1_0_mc_resume(struct amdgpu_device *adev)
|
|
lower_32_bits(adev->vcn.gpu_addr));
|
|
lower_32_bits(adev->vcn.gpu_addr));
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
|
|
upper_32_bits(adev->vcn.gpu_addr));
|
|
upper_32_bits(adev->vcn.gpu_addr));
|
|
- WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0);
|
|
|
|
|
|
+ WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
|
|
|
|
+ AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size);
|
|
|
|
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
|
|
WREG32(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
|