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@@ -18,11 +18,25 @@ struct hv_flush_pcpu {
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u64 gva_list[];
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u64 gva_list[];
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};
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};
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+/* HvFlushVirtualAddressSpaceEx, HvFlushVirtualAddressListEx hypercalls */
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+struct hv_flush_pcpu_ex {
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+ u64 address_space;
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+ u64 flags;
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+ struct {
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+ u64 format;
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+ u64 valid_bank_mask;
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+ u64 bank_contents[];
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+ } hv_vp_set;
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+ u64 gva_list[];
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+};
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+
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/* Each gva in gva_list encodes up to 4096 pages to flush */
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/* Each gva in gva_list encodes up to 4096 pages to flush */
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#define HV_TLB_FLUSH_UNIT (4096 * PAGE_SIZE)
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#define HV_TLB_FLUSH_UNIT (4096 * PAGE_SIZE)
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static struct hv_flush_pcpu __percpu *pcpu_flush;
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static struct hv_flush_pcpu __percpu *pcpu_flush;
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+static struct hv_flush_pcpu_ex __percpu *pcpu_flush_ex;
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+
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/*
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/*
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* Fills in gva_list starting from offset. Returns the number of items added.
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* Fills in gva_list starting from offset. Returns the number of items added.
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*/
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*/
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@@ -53,6 +67,34 @@ static inline int fill_gva_list(u64 gva_list[], int offset,
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return gva_n - offset;
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return gva_n - offset;
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}
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}
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+/* Return the number of banks in the resulting vp_set */
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+static inline int cpumask_to_vp_set(struct hv_flush_pcpu_ex *flush,
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+ const struct cpumask *cpus)
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+{
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+ int cpu, vcpu, vcpu_bank, vcpu_offset, nr_bank = 1;
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+
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+ /*
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+ * Some banks may end up being empty but this is acceptable.
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+ */
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+ for_each_cpu(cpu, cpus) {
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+ vcpu = hv_cpu_number_to_vp_number(cpu);
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+ vcpu_bank = vcpu / 64;
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+ vcpu_offset = vcpu % 64;
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+
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+ /* valid_bank_mask can represent up to 64 banks */
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+ if (vcpu_bank >= 64)
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+ return 0;
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+
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+ __set_bit(vcpu_offset, (unsigned long *)
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+ &flush->hv_vp_set.bank_contents[vcpu_bank]);
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+ if (vcpu_bank >= nr_bank)
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+ nr_bank = vcpu_bank + 1;
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+ }
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+ flush->hv_vp_set.valid_bank_mask = GENMASK_ULL(nr_bank - 1, 0);
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+
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+ return nr_bank;
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+}
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+
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static void hyperv_flush_tlb_others(const struct cpumask *cpus,
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static void hyperv_flush_tlb_others(const struct cpumask *cpus,
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const struct flush_tlb_info *info)
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const struct flush_tlb_info *info)
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{
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{
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@@ -122,17 +164,102 @@ do_native:
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native_flush_tlb_others(cpus, info);
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native_flush_tlb_others(cpus, info);
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}
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}
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+static void hyperv_flush_tlb_others_ex(const struct cpumask *cpus,
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+ const struct flush_tlb_info *info)
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+{
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+ int nr_bank = 0, max_gvas, gva_n;
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+ struct hv_flush_pcpu_ex *flush;
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+ u64 status = U64_MAX;
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+ unsigned long flags;
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+
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+ if (!pcpu_flush_ex || !hv_hypercall_pg)
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+ goto do_native;
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+
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+ if (cpumask_empty(cpus))
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+ return;
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+
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+ local_irq_save(flags);
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+
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+ flush = this_cpu_ptr(pcpu_flush_ex);
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+
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+ if (info->mm) {
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+ flush->address_space = virt_to_phys(info->mm->pgd);
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+ flush->flags = 0;
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+ } else {
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+ flush->address_space = 0;
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+ flush->flags = HV_FLUSH_ALL_VIRTUAL_ADDRESS_SPACES;
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+ }
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+
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+ flush->hv_vp_set.valid_bank_mask = 0;
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+
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+ if (!cpumask_equal(cpus, cpu_present_mask)) {
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+ flush->hv_vp_set.format = HV_GENERIC_SET_SPARCE_4K;
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+ nr_bank = cpumask_to_vp_set(flush, cpus);
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+ }
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+
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+ if (!nr_bank) {
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+ flush->hv_vp_set.format = HV_GENERIC_SET_ALL;
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+ flush->flags |= HV_FLUSH_ALL_PROCESSORS;
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+ }
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+
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+ /*
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+ * We can flush not more than max_gvas with one hypercall. Flush the
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+ * whole address space if we were asked to do more.
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+ */
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+ max_gvas =
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+ (PAGE_SIZE - sizeof(*flush) - nr_bank *
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+ sizeof(flush->hv_vp_set.bank_contents[0])) /
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+ sizeof(flush->gva_list[0]);
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+
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+ if (info->end == TLB_FLUSH_ALL) {
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+ flush->flags |= HV_FLUSH_NON_GLOBAL_MAPPINGS_ONLY;
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+ status = hv_do_rep_hypercall(
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+ HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX,
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+ 0, nr_bank + 2, flush, NULL);
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+ } else if (info->end &&
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+ ((info->end - info->start)/HV_TLB_FLUSH_UNIT) > max_gvas) {
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+ status = hv_do_rep_hypercall(
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+ HVCALL_FLUSH_VIRTUAL_ADDRESS_SPACE_EX,
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+ 0, nr_bank + 2, flush, NULL);
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+ } else {
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+ gva_n = fill_gva_list(flush->gva_list, nr_bank,
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+ info->start, info->end);
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+ status = hv_do_rep_hypercall(
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+ HVCALL_FLUSH_VIRTUAL_ADDRESS_LIST_EX,
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+ gva_n, nr_bank + 2, flush, NULL);
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+ }
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+
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+ local_irq_restore(flags);
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+
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+ if (!(status & HV_HYPERCALL_RESULT_MASK))
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+ return;
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+do_native:
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+ native_flush_tlb_others(cpus, info);
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+}
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+
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void hyperv_setup_mmu_ops(void)
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void hyperv_setup_mmu_ops(void)
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{
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{
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- if (ms_hyperv.hints & HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED) {
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+ if (!(ms_hyperv.hints & HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED))
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+ return;
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+
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+ setup_clear_cpu_cap(X86_FEATURE_PCID);
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+
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+ if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED)) {
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pr_info("Using hypercall for remote TLB flush\n");
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pr_info("Using hypercall for remote TLB flush\n");
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pv_mmu_ops.flush_tlb_others = hyperv_flush_tlb_others;
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pv_mmu_ops.flush_tlb_others = hyperv_flush_tlb_others;
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- setup_clear_cpu_cap(X86_FEATURE_PCID);
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+ } else {
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+ pr_info("Using ext hypercall for remote TLB flush\n");
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+ pv_mmu_ops.flush_tlb_others = hyperv_flush_tlb_others_ex;
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}
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}
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}
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}
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void hyper_alloc_mmu(void)
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void hyper_alloc_mmu(void)
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{
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{
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- if (ms_hyperv.hints & HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED)
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+ if (!(ms_hyperv.hints & HV_X64_REMOTE_TLB_FLUSH_RECOMMENDED))
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+ return;
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+
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+ if (!(ms_hyperv.hints & HV_X64_EX_PROCESSOR_MASKS_RECOMMENDED))
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pcpu_flush = __alloc_percpu(PAGE_SIZE, PAGE_SIZE);
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pcpu_flush = __alloc_percpu(PAGE_SIZE, PAGE_SIZE);
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+ else
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+ pcpu_flush_ex = __alloc_percpu(PAGE_SIZE, PAGE_SIZE);
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}
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}
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